Towards logical entanglement creation in trivalent planar architectures

Technical Summary: Towards Logical Entanglement Creation in Trivalent Planar Architectures

Problem Statement
Scalable quantum computation requires low-overhead quantum error correction (QEC) to protect logical qubits. While the surface code is the leading paradigm for planar architectures, its conventional implementation relies on four-valent connectivity (each physical qubit interacting with four neighbors), imposing demanding hardware constraints on superconducting platforms. Recent work has demonstrated that a trivalent (degree-three) connectivity is sufficient for fault-tolerant QEC. However, the application of trivalent designs to logical operations, specifically lattice surgery for entanglement generation, had not been explored. The challenge lies in adapting lattice surgery protocols to trivalent layouts while minimizing resource overhead and maintaining logical fidelity under realistic noise conditions.

Methodology
The authors develop and analyze a trivalent lattice-surgery scheme for the rotated surface code on planar qubit layouts. Their approach involves three main components:

1. Circuit Construction: They introduce a scalable circuit construction for trivalent lattice surgery that operates without requiring additional data qubits in the intermediate region between logical patches. This contrasts with four-valent schemes which typically require a stripe of $d$ additional data qubits to maintain modularity.
2. Noise Modeling: The study benchmarks logical fidelity using two noise models:
   • A standard circuit-level noise model where errors occur with probability $p$ on gates, measurements, and initializations.
   • An experimentally motivated noise model based on superconducting transmon and fluxonium parameters (referencing Ref. [7]), which includes idling noise (amplitude damping and dephasing) during finite-duration gate and measurement times.
3. Simulation and Benchmarking: The authors simulate quantum memory experiments and logical state teleportation (via lattice surgery) for code distances $d=3, 5, 7$. They compare the trivalent scheme against the four-valent baseline, analyzing logical error rates, resource counts (qubits and gates), and the impact of potential hardware improvements, such as reduced two-qubit gate times enabled by lower connectivity.

Key Contributions

• Trivalent Lattice Surgery Protocol: The paper presents a specific protocol for merging and splitting surface code patches in a trivalent architecture. Crucially, this protocol eliminates the need for the intermediate stripe of $d$ data qubits required in the minimal four-valent implementation, thereby reducing the qubit overhead by $O(d)$ and the two-qubit gate count by $O(d)$ relative to the total $O(d^2)$ and $O(d^3)$ resources, respectively.
• Resource Analysis: The authors quantify the resource savings, showing that the trivalent design requires zero additional data qubits and one additional ancilla qubit for the merging operation, compared to $d$ data and $d+1$ ancilla qubits in the four-valent case.
• Noise Sensitivity Analysis: The study identifies a structural disadvantage in the trivalent scheme under realistic noise models. Due to the altered circuit structure and error propagation paths, the trivalent scheme exhibits a slightly higher logical error rate than the four-valent scheme when idling noise is significant.
• Hardware Trade-off Modeling: The authors model the potential benefits of reduced valency on hardware performance, specifically for fluxonium qubits. They posit that reducing connectivity allows for better distribution of capacitance, potentially increasing coupling strength and reducing gate times. They simulate this by scaling gate times and analyzing the resulting logical error rates.

Results

• Quantum Memory: Under a standard noise model (neglecting gate durations), the trivalent and four-valent schemes exhibit very similar logical error rates. However, when an experimentally motivated noise model including idling errors is applied, the trivalent scheme shows a slightly elevated logical error rate compared to the four-valent scheme.
• Lattice Surgery (Teleportation):
  • Under the standard noise model, the trivalent lattice surgery shows a logical error rate improvement of approximately 2% for $d=3$, attributed to the reduction in the leading-order prefactor of the error rate due to fewer gates.
  • Under the experimentally motivated noise model without hardware improvements, the trivalent scheme performs worse than the four-valent scheme for $d=5$ and $d=7$, though it shows a marginal improvement for $d=3$ due to the overhead reduction.
  • Gate Time Improvement: When the authors model a reduction in two-qubit gate time (by a factor $\eta$) enabled by the trivalent hardware constraints, the trivalent scheme demonstrates a potential improvement in logical fidelity of up to 25% for distance-three memory and up to 50% for lattice-surgery-based teleportation. This improvement depends on the extent to which gate infidelity is rooted in decoherence (parameter $\alpha$).

Significance and Claims
The paper claims that trivalent planar architectures offer a viable path toward scalable logical quantum processors based on the surface code. The significance of the work lies in demonstrating that:

1. Trivalent lattice surgery can be implemented with reduced resource overhead compared to four-valent schemes, specifically by removing the need for intermediate data qubits.
2. While the trivalent circuit design carries a structural disadvantage under realistic idling noise, this disadvantage may be compensated or overcompensated by hardware-level benefits inherent to lower-connectivity architectures (e.g., improved gate speeds and fidelities in fluxonium systems).
3. The trade-off between circuit-level scheduling costs (structural disadvantage) and hardware-level benefits (reduced connectivity) suggests that trivalent layouts are particularly promising for specific superconducting qubit implementations where connectivity constraints are a primary bottleneck.

The authors conclude that the overall utility of trivalent operation requires balancing these circuit-level and hardware-level factors, and they identify future work in studying these schemes under more specific hardware noise models and in larger logical processors.