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EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysis

EDATracer is an agentic framework that leverages a knowledge graph and semantic vector index to enable large-scale, evidence-grounded analysis of heterogeneous EDA artifacts, outperforming existing tools on a new 90-question benchmark derived from a 2,787-design dataset while using significantly fewer tokens.

Original authors: Phat Tieu, Sayanti Jana, Matthew DeLorenzo, Jiawen Wu, Narendran Srinivasan, Srinivas Shakkottai, Jiang Hu, Jeyavijayan Rajendran

Published 2026-08-06

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CC BY 4.0

Original authors: Phat Tieu, Sayanti Jana, Matthew DeLorenzo, Jiawen Wu, Narendran Srinivasan, Srinivas Shakkottai, Jiang Hu, Jeyavijayan Rajendran

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine trying to fix a broken car, but instead of a single engine, you have a million scattered pieces: the blueprints, the mechanic's handwritten notes, the factory's computer logs, the list of every bolt used, and a report on how much fuel the engine should have used. Now, imagine that the car is a computer chip, and the "mechanic" is a super-smart computer program (an AI) trying to figure out why the car won't start. This is the daily reality for engineers designing modern chips. They rely on Electronic Design Automation (EDA) tools, which are like giant, automated factories that turn code into physical chip designs. These tools generate mountains of different files—logs, scripts, reports, and code—that are all connected but scattered across different folders.

The problem is that finding a specific clue in this digital haystack is incredibly hard. If a chip fails, the error might be mentioned in a log file, but the cause could be hidden in a source code file or a timing report from a different stage of the design. Traditional AI tools often get lost in this mess, guessing answers or missing the connection between the files. This paper introduces a new way to help these AI detectives solve the mystery without getting overwhelmed by the sheer volume of data.

The researchers from Texas A&M University have built a system called EDATracer. Think of EDATracer as a super-organized librarian for the chip design world. Instead of just dumping all the files into a pile and asking an AI to "read everything," EDATracer first builds a giant, interactive map (called a knowledge graph) of the entire chip project. This map connects the dots: it knows that a specific error in a log file is linked to a specific line of code, which is linked to a specific part of the chip's blueprint.

To test their idea, the team didn't just look at one or two designs; they gathered a massive collection of 2,787 different open-source chip designs. They ran these through synthesis tools to generate 18.9 GB of real-world artifacts, including logs, netlists (the gate-level blueprints), and performance reports. They then created a "test" consisting of 90 questions ranging from simple facts ("What is the area of this chip?") to complex reasoning ("Why did the timing fail?").

When they let EDATracer loose on these questions, it acted like a team of agents: one agent searched the map for clues, and another agent pieced those clues together to form an answer. The results were impressive. EDATracer was more accurate than popular commercial AI coding assistants like Cursor and Claude Code, getting the right answer 6.4% to 7.2% more often on average. Even better, it did this while using 2.0 to 3.2 times fewer "tokens" (the digital currency AI uses to think and speak), making it much more efficient.

The paper suggests that the key to this success wasn't just having a smarter AI brain, but giving that brain a better map. By grounding the AI's reasoning in a structured graph of evidence, EDATracer avoided the common trap of "hallucinating" (making things up) or missing the forest for the trees. While the system currently focuses on the synthesis stage of chip design, the authors show that organizing complex, scattered data into a connected web can turn a confused AI into a precise detective, solving problems that were previously too messy for computers to handle alone.

Technical Summary: EDATracer

Problem Statement

Modern semiconductor design relies heavily on Electronic Design Automation (EDA) tools, which generate vast, heterogeneous collections of artifacts including source code (RTL), synthesis scripts, logs, netlists, and Power-Performance-Area (PPA) reports. Analyzing these artifacts is critical for debugging, optimization, and understanding design flows. However, this process faces three primary challenges:

Lack of Benchmarks: Existing datasets focus on code generation or single-log analysis, lacking public benchmarks for large-scale, cross-artifact analysis where evidence is distributed across multiple file types and design stages.
Complexity and Scale: A single design can produce thousands of files and millions of lines of output. Full-context prompting is impractical due to token limits and the heterogeneity of the data.
Grounding Failures: Effective analysis often requires linking evidence from disparate sources (e.g., a failure message in a log file linked to a specific module in a source file or an earlier report). Without a reliable reference to the EDA tool context, Large Language Model (LLM) agents tend to hallucinate or rely on shallow keyword matches rather than grounded reasoning.

Methodology

The authors propose EDATracer, an agentic framework designed for evidence-grounded EDA artifact analysis. The system operates through two distinct stages:

1. Dataset Curation and Construction

To address the lack of public data, the authors constructed a comprehensive dataset comprising 2,787 synthesizable open-source chip designs and their associated EDA artifacts, totaling 18.9 GB.

Collection: A four-phase filtering process (discovery, heuristic filtering, LLM-based evaluation, and synthesis feasibility checks) was applied to public GitHub repositories to identify valid, synthesizable RTL designs.
Generation: An automated pipeline synthesized each design using industry-standard tools (Synopsys Design Compiler) and open-source technology libraries (NanGate45, SkyWater130, ASAP7). This process involved an iterative error repair loop to handle synthesis failures by adjusting top-module selection, clock signals, or script configurations.
Artifacts: The final dataset includes source code, synthesis scripts, logs, gate-level netlists, and PPA reports.

2. Agentic Framework Architecture

EDATracer organizes these artifacts into a structured representation to enable retrieval and reasoning:

Offline Stage (Knowledge Graph & Index):
- Knowledge Graph (KG): Artifacts are mapped into a typed knowledge graph ( $G$ ) where nodes represent entities (designs, modules, logs, reports) and edges encode hierarchy, provenance, and structural relationships.
- Semantic Vector Index: Text-bearing nodes (e.g., log chunks, documentation) are embedded and indexed ( $Z$ ) to support semantic search while maintaining links back to the graph structure.
Online Stage (Agentic Interaction):
- Retrieval Agent: Interacts with the user query to generate information requests. It utilizes two modes: Semantic Retrieval (vector search over text chunks) and Structured Retrieval (Cypher queries over the knowledge graph to extract specific metrics, relationships, or provenance).
- Reasoning Agent: Synthesizes the retrieved evidence. It iteratively assesses whether the accumulated context is sufficient to answer the query. If not, it requests further evidence; otherwise, it generates a grounded answer supported by specific artifacts.

Key Contributions

EDATracer Framework: An agentic system that combines a domain-specific knowledge graph with LLM reasoning to perform grounded, cross-artifact analysis of chip designs.
Large-Scale EDA Dataset: A curated dataset of 2,787 designs with 18.9 GB of heterogeneous artifacts, capturing design hierarchies and cross-artifact dependencies.
90-Question Benchmark: A manually verified benchmark covering factual, statistical, and reasoning tasks at varying difficulty levels to evaluate EDA artifact analysis capabilities.
Comprehensive Evaluation: A rigorous comparison against state-of-the-art commercial agents (Cursor, Claude Code) and various LLM backbones (Claude Opus, Sonnet, Haiku, GPT-5, Qwen).

Results

The evaluation demonstrates that EDATracer outperforms existing commercial agentic frameworks in both accuracy and efficiency:

Accuracy: EDATracer achieved the best overall pass@1 accuracy, outperforming Cursor by an average of 6.4 percentage points and Claude Code by 7.2 percentage points. The system showed particular strength in statistical questions, where it successfully aggregated data from multiple artifacts while preserving correct units and prefixes.
Efficiency: EDATracer utilized 2.0× to 3.2× fewer tokens than Cursor and Claude Code. This reduction is attributed to the structured retrieval mechanism, which avoids passing large, irrelevant contexts to the LLM and instead retrieves targeted graph nodes and relationships.
Local Deployment: The framework enabled smaller, open-weight models (e.g., Qwen 3.5-9B) to perform effectively on factual and statistical tasks, approaching the performance of larger proprietary models when grounded by the knowledge graph.

Significance and Claims

The paper positions EDATracer as a solution to the practical bottleneck of EDA artifact analysis in modern chip design. The authors claim that by organizing heterogeneous artifacts into a structured knowledge graph, the framework enables LLM agents to perform grounded reasoning rather than relying on hallucination or shallow pattern matching.

The significance lies in demonstrating that graph-based retrieval can significantly improve the cost-efficiency and accuracy of LLM-based EDA analysis. The authors note that while the current framework focuses on synthesis-stage artifacts, the methodology provides a foundation for extending analysis to broader design-flow stages (floorplanning, routing, sign-off) and multimodal artifacts (layouts, waveforms) in future work. The paper emphasizes that the structured representation is crucial for linking evidence across the design flow, a capability that flat retrieval-augmented generation (RAG) approaches lack.