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A high-isolation wideband channelizer for MKID readouts: a custom HLS implementation on RFSoC

This paper presents a high-isolation, wideband MKID channelizer implemented on a Xilinx Zynq UltraScale+ RFSoC using a custom Vitis HLS and VHDL design that achieves superior spectral performance through a 50% overlapping polyphase filter bank and a split-path architecture operating at a robust 256 MHz.

Original authors: Alberto Hernandez Fernandez, David Diaz Martin, Jose Javier Diaz Garcia, Roger John Hoyland, Luis Fernando Rodriguez Ramos, Diego Portero Rodriguez, Silvestre Rodriguez Perez

Published 2026-08-26

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CC BY 4.0

Original authors: Alberto Hernandez Fernandez, David Diaz Martin, Jose Javier Diaz Garcia, Roger John Hoyland, Luis Fernando Rodriguez Ramos, Diego Portero Rodriguez, Silvestre Rodriguez Perez

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

In the quiet, frigid depths of space, a new kind of telescope is learning to see the universe not just as a picture, but as a symphony of individual photons. These instruments rely on thousands of tiny superconducting sensors, each tuned to a specific frequency like a unique radio station. When a single particle of light strikes a sensor, it causes a subtle shift in that sensor's frequency, a whisper that tells astronomers exactly what kind of energy arrived and when. To hear this whisper, the sensors are all connected to a single wire, and the challenge is to listen to thousands of them at once without the signals blurring into noise. This is the art of frequency-division multiplexing, a method that allows a single cable to carry the voices of an entire array of detectors. However, just as a crowded room makes it hard to hear a single voice, the sheer density of these sensors creates a problem where the edges of their frequency channels overlap, causing a loss of sensitivity and a distortion of the signal.

A team of researchers at the Instituto de Astrofísica de Canarias has engineered a solution to this problem, creating a highly precise digital filter that can separate these crowded signals with remarkable clarity. They built a custom system on a powerful chip known as an RFSoC, which acts as the brain for these detectors. Instead of trying to process the data as fast as possible by pushing the chip to its absolute speed limit, the team chose a different path: they built a wider, more parallel machine. By running the system at a steady, manageable speed and using two sets of filters working side-by-side, they were able to double the depth of their signal processing. This architectural choice allowed them to eliminate a specific type of signal loss known as scalloping loss, where tones falling between channels would otherwise be weakened by nearly four decibels. Their new design recovers that lost sensitivity, ensuring that every photon is counted with equal precision, regardless of where it lands in the frequency spectrum.

The core of this achievement lies in how the researchers organized the flow of data. In previous high-speed designs, engineers often tried to squeeze more performance out of a single filter by running it at extremely high speeds, clocking the chip at 512 million cycles per second. While this worked for smaller systems, it forced the filters to be shallow, meaning they could not effectively block out interference from neighboring channels. The new design rejects this trade-off. Instead of one fast filter, the team implemented two parallel filters running at a more robust 256 million cycles per second. This split-path approach allowed them to use a much deeper filter, one with sixteen taps compared to the eight taps used in similar high-speed systems. In the world of signal processing, a deeper filter acts like a sharper knife, cutting away unwanted noise and leaving the desired signal clean. This extra depth improved the isolation between channels by roughly fifteen decibels, a significant gain that prevents the signals from one sensor from bleeding into its neighbor.

To make this parallel system work, the researchers had to solve a complex puzzle of data reordering. Because the system processes data in overlapping chunks to ensure no gaps in coverage, the order in which the information arrives must be shuffled before it is analyzed. The team developed a custom engine to handle this shuffling, but they discovered a subtle trap in the way modern computer tools automatically build these circuits. The software, designed to speed up the process, sometimes placed two critical control signals into different stages of the processing pipeline, causing them to fall out of sync by a single clock cycle. This tiny delay was invisible in standard tests but would have corrupted the final data. The researchers fixed this by forcing the software to treat these signals as a single, inseparable unit, ensuring they changed state at the exact same moment. This discovery highlights a hidden hazard in using automated design tools, a lesson that will be valuable for others building similar high-performance systems.

The team validated their design through rigorous simulation and by testing the parent system in a cryogenic environment. They ran the system with a real array of superconducting detectors cooled to near absolute zero in a specialized refrigerator. In these tests, the system successfully identified individual resonators in total darkness, proving that the entire chain—from the arrival of a photon to the digital readout—works as intended. The simulations showed that the new channelizer delivers a flat, uniform response across the entire bandwidth, removing the blind spots that plagued earlier designs. When they swept a test signal across the frequency range, the system maintained a consistent sensitivity, with the signal strength remaining stable to within a tenth of a decibel. This level of precision is crucial for the next generation of astronomical instruments, which aim to detect the faintest signals from the early universe or the atmospheres of distant exoplanets.

This work represents a shift in how high-performance digital systems are built for science. Rather than relying on off-the-shelf components or pushing hardware to its breaking point, the researchers demonstrated that a custom approach, prioritizing architectural parallelism over raw speed, can yield superior results. By carefully managing the flow of data and investing the saved time margin into deeper, more precise filters, they created a system that is both resource-efficient and highly isolated. The result is a benchmark for wideband frequency-division multiplexed readouts, offering a clear path forward for instruments that need to listen to thousands of voices at once without missing a single word. As the team moves to integrate this design into their operational systems, the promise is a new era of sensitivity for telescopes that can hear the universe with unprecedented clarity.

Technical Summary: A High-Isolation Wideband Channelizer for MKID Readouts

Problem Statement
Microwave Kinetic Inductance Detectors (MKIDs) rely on Frequency-Division Multiplexing (FDM) to read out thousands of superconducting resonators simultaneously. The digital backend must separate the wideband digitized stream into individual resonator channels. Standard Polyphase Filter Banks (PFB) followed by an FFT reduce computational complexity from $O(M^2)$ to $O(M \log M)$ . However, critically sampled PFBs suffer from "scalloping loss," where signals falling between FFT bins are attenuated by up to 3.9 dB, degrading sensitivity. The established remedy is an oversampled, 50% overlapping PFB (OPFB).

Implementing an OPFB at multi-gigahertz sampling rates (e.g., 4.096 GSPS) on Field-Programmable Gate Arrays (FPGAs) presents a significant engineering challenge. State-of-the-art designs, such as those by Smith et al. (UCSB), achieve throughput by aggressively clocking the entire fabric (e.g., 512 MHz) and time-multiplexing a single physical filter. While compact, this approach constrains the prototype filter depth to shallow values (typically 8 taps), limiting channel isolation. For dense MKID arrays, where crosstalk between adjacent resonators must be suppressed, deeper filters with sharper transition bands are required, but they often fail to meet timing closure at high clock speeds.

Methodology
This work presents a custom channelizer implemented on a Xilinx Zynq UltraScale+ RFSoC (ZCU111) that prioritizes architectural parallelism over raw clock speed. The design processes a 4.096 GSPS input stream with a per-branch super-sample rate (SSR) of 16.

Split-Path Topology: Instead of time-multiplexing a single filter at 512 MHz, the design computes delayed and non-delayed polyphase branches concurrently using two physically parallel FIR branches. This allows the bulk of the channelizer (polyphase banks and reordering) to operate at a robust 256 MHz.
Frame-Level Reordering: To achieve the required 50% overlap, the design employs a frame-level reordering scheme rather than sample-level interleaving. The two parallel branches feed a reordering engine that alternates whole frames between "LOWER" and "UPPER" sub-bands. This preserves a pipeline initiation interval (II) of 1 without requiring the entire datapath to run at 512 MHz.
Hybrid Implementation: The design is primarily written in Vitis High-Level Synthesis (HLS) using C++, with the time-critical output serializer and glue logic implemented in VHDL.
Deep Filter Design: The freed timing budget from the 256 MHz operation is invested in a 16-tap Blackman prototype filter, doubling the depth of comparable high-speed systems.
Clock Domain Management: The architecture is partitioned into two zones: a main 256 MHz domain for the polyphase banks and reordering, and a minimal 512 MHz subdomain confined to the BRAM-to-FFT section. This avoids the timing closure failures associated with running the entire deep-filter chain at 512 MHz.

Key Contributions and Implementation Insights
The paper details the complete internal architecture of the reordering engine and reports two specific implementation hazards encountered during HLS development that are not documented in prior literature:

Pipeline-Stage Skew: In the original HLS source, state toggles for frame boundaries were placed in adjacent source-level if blocks. The HLS compiler scheduled these into different pipeline stages, causing a one-cycle skew where the buffer selection and overlap state were desynchronized. The fix required grouping all state updates into a single unified expression to ensure atomic scheduling.
Selective Soft Reset: To ensure the channelizer can be restarted without losing frame alignment, the authors implemented a selective reset policy. On a stop command, only the "first frame done" flag is cleared, while critical state variables (write pointers, ping-pong selectors, and frame states) are preserved. This maintains the phase relationship between the reorder engine and the input stream.

Results

Simulation: The design was validated via a cycle-accurate Xsim testbench. The 2/1 overlapped architecture successfully recovered the ~3.9 dB scalloping loss, flattening the channel response to below 0.1 dB across the full 2 MHz channel.
Channel Isolation: The 16-tap prototype filter provides a stop-band approximately 15 dB deeper than an 8-tap design at the first adjacent channel, significantly improving inter-channel isolation.
Batch Characterization: A systematic sweep of 100 independent tones confirmed symmetric adjacent-channel responses and an out-of-band leakage floor of ~80 dB.
Cryogenic Operation: The parent readout system (using the non-overlapped PFB) has been operated on a real MKID array (IAC-1) in an adiabatic demagnetization refrigerator (ADR) at ~100 mK, successfully identifying individual resonators in total darkness. This validates the end-to-end RF-digital-RF loop for the future deployment of the overlapped channelizer.
Resource Utilization: The design utilizes 512 DSP48E2 slices (12% of the device) and roughly one-third of the Block RAM. All modules meet timing at their target clocks with positive slack.

Significance
The paper claims that this work demonstrates that architectural parallelism can be traded against clock speed to achieve a deeper, higher-isolation channelizer than aggressively clocked, IP-based designs of comparable bandwidth. By utilizing a split-path, frame-level approach, the design achieves a 16-tap filter depth on a single RFSoC at 4.096 GSPS, a feat not previously reported for this class of devices. The work serves as a resource-efficient, high-isolation benchmark for wideband FDM readouts and documents specific HLS implementation strategies (frame-level reordering, handling state skew, and selective resets) that enable such designs to be synthesizable and operable. The authors position this as a complementary approach to existing time-multiplexed designs, offering superior isolation for dense arrays where crosstalk is the limiting systematic.

Technical Summary: A High-Isolation Wideband Channelizer for MKID Readouts

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