⚛️ quantum physics

High-Throughput Normalized Min-Sum Belief Propagation Decoding for Quantum LDPC Codes with Near-Memory Processing

This paper demonstrates that a DPU-based Processing-in-Memory architecture can achieve an 8.8x throughput improvement and sub-millisecond latency for high-throughput, normalized Min-Sum Belief Propagation decoding of quantum LDPC codes, effectively meeting the real-time error correction requirements for trapped-ion quantum computers.

Original authors: Jeonggeun Seo, Youngsun Han, Leanghok Hour, Dongmin Kim

Published 2026-08-31

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CC BY 4.0

Original authors: Jeonggeun Seo, Youngsun Han, Leanghok Hour, Dongmin Kim

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Quantum computers hold the promise of solving problems that are currently impossible for even the most powerful supercomputers, from designing new medicines to cracking complex encryption. However, these machines are incredibly fragile. The delicate quantum information they carry is easily scrambled by the slightest disturbance from the environment, a phenomenon known as noise. To keep a quantum computer running, scientists must constantly monitor for these errors and fix them before they destroy the calculation. This process, called quantum error correction, acts like a relentless guardian, checking the system's health thousands of times per second and applying tiny adjustments to keep the data intact.

For this guardian to work, it needs a classical computer to act as its brain. This classical computer must read the error signals, figure out what went wrong, and decide how to fix it, all within a tiny fraction of a second. If the classical computer is too slow, the quantum computer will fail before the correction can be applied. As quantum machines grow larger and more complex, the amount of data this classical brain needs to process explodes, creating a massive bottleneck. The challenge is not just to be fast, but to be predictably fast, ensuring that no single error check ever takes too long and causes a backlog that crashes the system.

Researchers at Pukyong National University in South Korea have tackled this bottleneck by rethinking how the classical computer handles these error checks. They focused on a specific type of error-correcting code known as a quantum low-density parity-check code, which is designed to be efficient for large-scale quantum machines. To decode the error signals from these codes, they developed a new system that moves the heavy lifting of calculation directly into the memory chips where the data lives, rather than shuttling data back and forth to a central processor. This approach, known as near-memory processing, allows the system to keep the data right next to the tools needed to fix it, drastically reducing the time spent waiting for information to travel.

The team tested their idea using a specialized architecture called a Data Processing Unit, or DPU, which integrates small, efficient processors directly into memory modules. They mapped the complex math required to decode a specific quantum code onto this hardware. Instead of relying on a traditional computer processor, they distributed the work across thousands of these DPUs. Within each unit, they split the decoding task among eleven smaller threads of work, allowing them to process different parts of the error signal simultaneously. Meanwhile, thousands of these units worked in parallel, each handling a separate error check, creating a massive, coordinated effort to solve the puzzle of quantum errors.

The results of their simulation were striking. When they compared their new system to a standard computer setup using sixteen logical processors, the new architecture was nearly nine times faster at processing error signals. At a specific error rate, the system could decode over ten million error checks per second, compared to just over one million for the traditional setup. This speed advantage held steady even as the complexity of the decoding process increased. More importantly, the system proved to be remarkably consistent. In real-time quantum computing, it is not enough to be fast on average; the system must never have a "bad day" where a single check takes too long. The researchers found that even in the worst-case scenarios they simulated, the time it took to process a single error check never exceeded one millisecond. In fact, the time was so predictable that the variation between the fastest and slowest checks was less than one percent of the total time.

This consistency is crucial for the specific type of quantum computer known as a trapped-ion system, which operates on a timescale where a one-millisecond window is the standard limit for error correction. The study showed that their design could comfortably stay within this limit, even when running multiple rounds of calculation to improve accuracy. The researchers also observed a clear trade-off: running more rounds of calculation to get a more accurate result naturally took more time, but the system could still deliver the most accurate results within the required time limit. By balancing the number of calculation rounds with the available time, the system could maintain high accuracy without risking a delay that would break the quantum computer.

The work demonstrates that moving computation closer to memory is a viable path forward for the future of quantum error correction. By keeping the data local and processing it in parallel across thousands of units, the researchers showed that it is possible to handle the massive data demands of large-scale quantum computers without sacrificing speed or reliability. While the results come from a simulation rather than a physical machine, the findings provide a strong blueprint for building the classical brains that will be needed to keep the next generation of quantum computers running smoothly. The study confirms that with the right architecture, the classical computer can keep pace with the quantum machine, ensuring that the guardian never sleeps and the calculation never fails.

Technical Summary: High-Throughput Normalized Min-Sum Belief Propagation Decoding for Quantum LDPC Codes with Near-Memory Processing

Problem Statement
As fault-tolerant quantum computing (FTQC) systems scale, classical decoders face increasing demands to process syndrome information within strict timing budgets per error correction cycle. Quantum Low-Density Parity-Check (qLDPC) codes offer high encoding rates and reduced physical qubit overhead but rely on iterative Belief Propagation (BP) decoding. This decoding process involves repeated message updates over sparse Tanner graphs, creating substantial memory-access and data movement demands. The execution pattern of BP—characterized by sparse arithmetic combined with frequent, repeated memory accesses—makes data locality and parallel processing critical architectural considerations. Traditional CPU-based approaches struggle to balance the high throughput required for scaling with the low, predictable latency necessary for real-time quantum error correction (QEC), particularly in trapped-ion platforms where decoder timing budgets are on the order of milliseconds.

Methodology
The authors propose a near-memory processing (NMP) solution using a Data Processing Unit (DPU)-based Processing-in-Memory (PIM) architecture to decode the [[144, 12, 12]] Bivariate Bicycle qLDPC code. The design leverages the UPMEM PIM platform, which integrates lightweight processing cores (DPUs) directly with DRAM.

Algorithm Adaptation: The system implements a Normalized Min-Sum BP algorithm. This formulation replaces complex nonlinear functions (e.g., tanh) with integer-oriented operations (sign evaluation, minimum-magnitude selection, and fixed-point scaling). A normalization factor of $\alpha = 0.75$ is used, allowing the scaling step to be executed via integer addition and bit-shifting, which aligns with the DPU's integer execution pipeline.
Workload Partitioning:
- Intra-DPU Parallelism: Within a single DPU, the check-node update workload for one syndrome instance is divided among 11 hardware threads (tasklets). These tasklets share the DPU's processing pipeline and local memory (WRAM). To manage data dependencies, the 72 check nodes are partitioned into three conflict-free "color groups." Tasklets process check nodes within a group concurrently, synchronizing at group boundaries to maintain the row-layered update schedule.
- Inter-DPU Parallelism: Independent syndrome instances are distributed across multiple DPUs (up to 2,560 in the evaluated configuration). Each DPU processes a unique syndrome instance without requiring inter-DPU synchronization during the BP computation, enabling massive system-level parallelism.
Memory Organization: Frequently accessed decoding states (messages and posterior reliabilities) are maintained in the DPU's local WRAM, while input/output data transfer between the host and DPU occurs via MRAM using DMA. This minimizes data movement costs associated with the host memory hierarchy.

Key Contributions

DPU-Based Execution Scheme: The paper proposes a specific mapping of normalized Min-Sum BP decoding for the [[144, 12, 12]] Bivariate Bicycle code onto a DPU-based PIM architecture, offloading computation from the host CPU to keep frequently accessed state near the processing units.
Two-Level Parallelism Strategy: The authors organize the decoding workload hierarchically: 11 tasklets within each DPU handle the check-node updates of a single syndrome, while thousands of DPUs process independent syndromes concurrently.
Comprehensive Evaluation: The study evaluates the proposed scheme against a 16-logical-CPU baseline using projected aggregate throughput, per-syndrome processing time, Logical Error Rate (LER), and tail latency.

Results
The evaluation was conducted using the uPIMulator simulator for the DPU architecture and a 16-logical-CPU baseline (Intel Xeon E5-2686 v4) under a Pauli error model with ideal syndrome measurements.

Throughput: At a physical error probability of $p = 0.001$ and one BP iteration, the 2,560-DPU configuration achieved an aggregate throughput of $1.071 \times 10^7$ decodes/s. This represents an 8.8× improvement over the CPU baseline ( $1.22 \times 10^6$ decodes/s). The throughput advantage was maintained (8.0×) even at ten BP iterations. Throughput was found to be primarily governed by the number of BP iterations and the degree of syndrome-instance parallelism, rather than the physical error probability.
Logical Error Rate (LER) vs. Latency Trade-off: Increasing BP iterations improved LER, with the most significant gains occurring between one and two iterations. From two iterations onward, the LER remained below the physical error probability for all tested values of $p$ . However, per-syndrome processing time increased almost linearly with iterations.
Latency and Real-Time Feasibility: The study focused on the 1 ms decoder-side timing reference relevant to trapped-ion QEC.
- For 1 to 5 BP iterations, the maximum sampled serialized X + Z DPU compute latency remained below 1 ms, reaching approximately 0.873 ms at five iterations.
- The DPU latency distribution was highly predictable, with standard deviations below 1% of the mean (e.g., 5.843 µs at $p=0.001$ for 5 iterations).
- In contrast, the CPU baseline exhibited a "long tail" in latency; while its median latency was low, the p99.9 and maximum sampled latencies exceeded the 1 ms threshold, indicating less predictability for real-time constraints.

Significance
The paper demonstrates that near-memory processing architectures, specifically DPU-based PIM, can effectively address the memory-bound nature of iterative qLDPC BP decoding. The proposed architecture successfully combines high aggregate throughput (scaling with the number of DPUs) with sub-millisecond, predictable decoder-kernel latency. These results suggest that such architectures are viable candidates for meeting the stringent timing and throughput requirements of real-time QEC in scalable fault-tolerant quantum systems, particularly for trapped-ion platforms where millisecond-scale decoder budgets are available. The work highlights the importance of selecting the BP iteration count to balance decoding performance (LER) against the available real-time processing budget.

Technical Summary: High-Throughput Normalized Min-Sum Belief Propagation Decoding for Quantum LDPC Codes with Near-Memory Processing

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