Multi-Branch Transport in a Back-gated WS$_2$ Transistor at Deep-Cryogenic Temperature

Technical Summary: Multi-Branch Transport in a Back-gated WS2 Transistor at Deep-Cryogenic Temperature

Problem and Motivation
Two-dimensional (2D) semiconductors, particularly transition-metal dichalcogenides (TMDCs) like tungsten disulphide (WS2), are promising candidates for next-generation electronics beyond conventional silicon. While their potential for room-temperature logic and flexible electronics is well-demonstrated, emerging technologies in space instrumentation, low-noise sensing, and quantum computing require devices to operate effectively at cryogenic temperatures. At these low temperatures, thermally activated transport is suppressed, potentially increasing sensitivity to contact barriers, trapped charges, and carrier localization. These factors can alter critical transistor parameters such as threshold voltage, hysteresis, and current modulation. Consequently, understanding the behavior of 2D field-effect transistors (FETs) under deep-cryogenic conditions is essential for assessing their suitability for quantum-compatible electronic systems.

Methodology
The authors electrically characterized a back-gated multilayer WS2 FET down to a temperature of 20 mK. The device was fabricated on a highly doped p++ silicon substrate (serving as the global back gate) with an 85-nm thermally grown SiO2 dielectric. WS2 flakes were mechanically exfoliated and transferred onto the substrate, with source and drain contacts defined lithographically using Ni/Au metallization. The flake thickness was determined via atomic force microscopy (AFM) to be approximately 90 nm.

Electrical measurements were conducted using an Oxford Instruments Proteox dilution refrigerator. The gate bias ($V_{GS}$) was applied via a source-measure unit (SMU), while the drain-source current ($I_{DS}$) was measured using a transimpedance amplifier (TIA) to ensure high sensitivity for low off-state currents. Transfer characteristics ($I_{DS}$ vs. $V_{GS}$) were recorded in both forward (FWD) and backward (BWD) sweep directions across a temperature range of 20 mK to 25 K, with additional data points at 77 K and room temperature.

Key Results

1. Gate Tunability and On/Off Ratio: The device remained strongly gate-tunable throughout the entire cryogenic regime. It achieved an effective on/off current ratio exceeding $10^5$ even at 20 mK, demonstrating robust switching performance and low off-state leakage in the millikelvin range.
2. Hysteresis Reduction: While gate-sweep hysteresis was observed, it was substantially reduced at cryogenic temperatures compared to room-temperature operation. This suggests improved threshold stability under deep-cryogenic conditions, likely due to the freezing of slow charge trapping and detrapping processes at the semiconductor/dielectric interface.
3. Multi-Stage Turn-On Behavior: A distinct feature of the low-temperature transfer characteristics was the observation of reproducible, shoulder-like features during the turn-on phase. Instead of a single sharp transition from the off-state to the on-state, the drain current exhibited a multi-stage increase with intermediate regimes.
4. Negative Transconductance: In the high-current regime, the transfer characteristics showed a reduction in current at large positive gate biases (negative transconductance), a behavior more pronounced under negative drain-source bias.

Modeling and Analysis
To explain the non-ideal, multi-stage turn-on behavior, the authors employed a phenomenological multi-branch Lambert-W model. This model treats the total drain current as the sum of multiple effective conduction branches operating in parallel, each with its own threshold voltage ($V_{th,m}$) and strength scaling factor ($K_m$).

• Branch Fitting: The data was best fitted using up to three effective branches at the lowest temperatures. The number of resolved branches decreased as temperature increased, suggesting that thermal broadening and increased carrier activation cause neighboring conduction contributions to merge into a single effective turn-on.
• Threshold Shifts: The extracted first-branch threshold voltage ($V_{th,1}$) shifted toward more negative gate voltages as temperature increased. This indicates that the effective onset of conduction occurs at a lower applied gate bias at higher temperatures, consistent with increased carrier activation. Conversely, the threshold voltage shifts toward more positive gate bias upon cooling.
• History Dependence: The number of branches required to fit the data and the specific threshold values differed between FWD and BWD sweeps, indicating that the channel electrostatics depend on the gate-bias history, likely due to charge trapping dynamics.

Significance and Claims
The paper claims that the observed multi-stage turn-on behavior can be interpreted as conduction established through several parallel transport contributions that activate over different gate-voltage ranges. This non-uniformity may arise from variations in gate coupling, carrier density, disorder, and interlayer coupling within the multilayer WS2 channel, potentially exacerbated by percolative transport at low temperatures. Density Functional Theory (DFT) calculations support the concept of field-induced spatial non-uniformity in multilayer WS2, where perpendicular electric fields redistribute band-edge states across the stack.

The authors conclude that the measured response is influenced by a combination of contact limitations, electrostatic disorder, and charge trapping at the WS2/SiO2 interface. While the device demonstrates strong gate control and high on/off ratios suitable for cryogenic applications, the presence of multi-branch transport and residual hysteresis suggests that future improvements in dielectric interfaces, contact resistance, and channel encapsulation are necessary to isolate intrinsic transport properties and stabilize device response for scalable cryogenic electronics.