FNO-Based Inverse Co-Design of Semiconducting Quantum-Dot Devices

Technical Summary: FNO-Based Inverse Co-Design of Semiconducting Quantum-Dot Devices

Problem Statement
Gate-defined semiconductor quantum dots (QDs) are critical building blocks for scalable spin-based quantum processors. However, their operational properties—such as confinement shape, position, and coupling—are highly sensitive to fabrication parameters (lithographic gate layout) and control parameters (applied voltages). While existing device architectures rely on iterative post-fabrication tuning, this approach is limited by the fixed lithographic layout; if the initial geometry cannot generate a suitable electrostatic landscape, optimal qubit properties (e.g., specific g-factors or Rabi frequencies) may remain inaccessible. Furthermore, exploring the design space via experimental fabrication is resource-intensive, while computational design using traditional physics-based simulators (e.g., Thomas–Fermi models) is computationally expensive and often lacks the differentiability required for gradient-based optimization.

Methodology
The authors propose a differentiable inverse co-design framework that jointly optimizes gate electrode geometries and applied voltages to achieve target QD confinement profiles. The methodology consists of three primary components:

1. Physics-Based Reference Data Generation:
   A semiclassical Thomas–Fermi electrostatic simulator is used to generate reference data. This model maps specific gate layouts and voltages to two-dimensional hole charge-density fields in Ge/SiGe heterostructures. The simulator accounts for surface gate potentials, background surface potentials, and self-consistent carrier screening.

2. Fourier Neural Operator (FNO) Surrogate:
   To overcome the computational cost and non-differentiability of the physics simulator, a Fourier Neural Operator (FNO) is trained as a surrogate model.

   • Input: A spatial field encoding the normalized gate voltages applied to specific electrode regions (with a background value for non-electrode areas).
   • Output: The corresponding 2D charge-density field.
   • Architecture: The FNO utilizes learned transformations of spatial Fourier modes to provide a global receptive field, essential for capturing non-local electrostatic responses.
   • Training: The model is trained on 30,000 configurations sampled from a wide range of gate geometries and voltages, including variations beyond experimentally accessible ranges to ensure robustness during optimization.

3. Differentiable Inverse Design Loop:
   The trained FNO is embedded within a gradient-based optimization loop.

   • Parameterization: Gate electrode edges are parameterized using Rectangular Edge Transformations (RET), defined by starting position ($R_{sp}$), tangential length ($R_l$), and oriented depth ($R_d$). Gate voltages ($V$) are also trainable.
   • Loss Function: The objective function ($L$) combines terms for target confinement ($L_{in}$, $L_{out}$) and fabrication constraints ($L_{ext}$, $L_{int}$).
     • $L_{in}$ and $L_{out}$ drive the charge density to match a target elliptical region and suppress density outside it.
     • $L_{ext}$ and $L_{int}$ enforce minimum spacing between electrodes and minimum electrode widths, respectively.
   • Optimization: Gradients of the total loss are backpropagated through the FNO and the differentiable geometry construction (using Straight-Through Estimators for discrete operations like "add" or "cut") to update both the continuous geometry parameters and voltages simultaneously.

Key Results

• Surrogate Accuracy: The FNO achieves a relative $L_2$ test error of 0.6% and a mean absolute error of approximately $2.5 \times 10^{13} \text{ m}^{-2}$. The model accurately reproduces the position, shape, and narrow density features of confined charge regions.
• Computational Efficiency: The FNO provides a massive speed-up compared to the CPU-based physics simulator. On a single NVIDIA H100 GPU, the FNO predicts charge density in 1.42 ms compared to 24.4 s for the simulator, representing a ~17,000-fold speed-up. With batched inference, this increases to ~24,000-fold.
• Inverse Design Success: Starting from the same initial device configuration, the framework successfully generated two distinct confinement geometries: vertically and horizontally elongated double quantum dots.
  • The optimized charge density covered >98% of the target elliptical regions while keeping density outside the targets below 2%.
  • Simultaneous and independent optimization strategies yielded comparable results, with gate geometry overlaps exceeding 95%.
• Validation: The final designs were verified using the original physics-based simulator. The resulting density profiles were visually indistinguishable from FNO predictions, with boundary differences of only 1–2 pixels (~1.5–3 nm), which is comparable to uncertainties arising from fabrication and material variations.

Significance and Claims
The paper claims to demonstrate a route toward pre-fabrication design of quantum devices with targeted operating properties. By co-optimizing gate geometry and voltages, the framework expands the accessible design space beyond what is possible through voltage tuning alone. The authors emphasize that this approach shifts the optimization burden from post-fabrication empirical tuning to pre-fabrication computational design.

While the current work uses confinement geometry as the direct design target, the authors note that the framework is modular and could be extended in the future to directly optimize quantum-mechanical properties (e.g., g-factor anisotropy, spin-orbit coupling) by integrating more advanced simulators. The successful application to Ge/SiGe double QDs suggests the approach is generalizable to other material systems and device architectures, potentially enabling the design of complex QD arrays where reproducible local device properties are essential.