Comprehensive TCAD Investigation of RF Performance, Noise Characteristics, and Intrinsic Capacitances of InAlAs/InGaAs/InP HEMTs: Impact of Gate-to-Channel Distance and Gate Bias.

Technical Summary: Comprehensive TCAD Investigation of RF Performance, Noise Characteristics, and Intrinsic Capacitances of InAlAs/InGaAs/InP HEMTs

Problem Statement
High Electron Mobility Transistors (HEMTs) are critical for next-generation ultra-high-frequency and high-speed electronic applications, with operating ranges extending into the terahertz domain. However, the continuous scaling of device dimensions and the pursuit of higher performance are constrained by several factors, including increased noise levels, reduced operational stability, and the growing influence of parasitic effects at high frequencies. Specifically, the impact of quantum phenomena (such as tunneling currents) and parasitic parameters on device reliability and performance remains a significant challenge. Noise, particularly channel noise arising from carrier transport, is a primary limiting factor for HEMT performance in high-frequency applications. There is a need to systematically understand how specific geometric parameters, such as the gate-to-channel distance (channel thickness), and operational parameters, such as gate bias, influence the electrical, noise, and capacitive characteristics of Indium Phosphide (InP)-based HEMTs.

Methodology
This study employs a comprehensive Technology Computer-Aided Design (TCAD) simulation approach using the SILVACO simulator to investigate an InAlAs/InGaAs/InP HEMT structure. The simulated device features a 30 nm gate length on an InP substrate with a specific layer stack including a semi-insulating substrate, an intrinsic buffer, a Si-delta-doped level, and a multi-layer channel structure (In0.7Ga0.3As/InAs/In0.53Ga0.47As) with varying thicknesses.

The study systematically varies two primary parameters:

1. Gate-to-Channel Distance ($h_{ch}$): Four distinct channel thicknesses are analyzed: 2 nm, 3 nm, 5 nm, and 7 nm.
2. Gate Bias ($V_{gs}$): Simulations are conducted across a range of gate voltages from 4 V to 8 V, with a fixed drain-source voltage ($V_{ds}$) of 2 V.

The physical modeling utilizes the Drift-Diffusion transport model, solving Poisson's equation, continuity equations, and transport equations. The investigation focuses on extracting and analyzing:

• Output conductance ($g_{ds}$).
• Input and output current and voltage noise spectral densities (both total and thermal components).
• Intrinsic parasitic capacitances ($C_{gs}$ and $C_{gd}$).
• RF performance metrics including transconductance and gain stability.

Key Contributions and Results

• Output Conductance ($g_{ds}$): The simulation results indicate that increasing the gate-to-channel distance leads to an increase in output conductance. This is attributed to the degradation of electrostatic gate control over the channel as the distance increases, enhancing drain-induced channel modulation. Conversely, reducing the distance (e.g., to 2 nm) suppresses channel-length modulation, lowering $g_{ds}$ and improving intrinsic voltage gain. Additionally, increasing the gate bias ($V_{gs}$) increases the output conductance, particularly at high frequencies, due to higher electron concentration in the 2DEG and dynamic transport effects.

• Noise Spectral Densities:

  • Current Noise: Both input and output current noise spectral densities decrease as the gate-to-channel distance increases. Increasing the gate bias ($V_{gs}$) results in an increase in the output current noise spectral density but a decrease in the input current noise spectral density. This suggests that while higher bias increases channel current fluctuations (output noise), it improves gate control, thereby reducing equivalent input noise.
  • Voltage Noise: The input and output voltage noise spectral densities exhibit saturation at high frequencies. Increasing the gate-to-channel distance effectively reduces the voltage noise spectral density. However, increasing the gate bias increases the output voltage noise spectral density while decreasing the input voltage noise spectral density.
  • Thermal Noise: Similar trends are observed for thermal noise components. The output current thermal noise increases with both gate-to-channel distance and gate bias, whereas the input current thermal noise decreases with both parameters. For voltage thermal noise, increasing the gate-to-channel distance reduces both input and output components, while increasing gate bias increases the output component but decreases the input component.

• Parasitic Capacitances: The analysis of intrinsic capacitances reveals that increasing the gate-to-channel distance increases the gate-to-source capacitance ($C_{gs}$) while decreasing the gate-to-drain capacitance ($C_{gd}$). The study notes that $C_{gs}$ remains consistently larger than $C_{gd}$, which is advantageous for high-frequency operation as it mitigates the Miller feedback effect. At higher gate biases, the electrostatic confinement of the 2DEG becomes the dominant factor, causing the capacitance curves for different channel thicknesses to converge.

• Frequency Response: The device exhibits quasi-static behavior at low frequencies (below $10^{10}$ Hz), where output conductance is constant. Above this threshold, conductance and noise characteristics are significantly influenced by parasitic capacitances and carrier transit effects. At ultra-high frequencies (approaching $10^{12}$–$10^{13}$ Hz), noise spectra tend to converge, indicating a dominance of intrinsic thermal fluctuations over geometry-dependent low-frequency mechanisms.

Significance and Claims
The paper claims that the simultaneous optimization of gate-to-channel distance, gate bias, and channel thickness provides an effective strategy for enhancing the electrical and high-frequency performance of InAlAs/InGaAs/InP HEMTs. Specifically, the study concludes that:

1. Reducing the gate-to-channel distance enhances electrostatic control, lowering output conductance and improving RF performance.
2. Increasing channel thickness effectively suppresses current and voltage noise by reducing the influence of interface trap states and lowering equivalent channel resistance.
3. Thicker-channel devices exhibit more stable high-frequency behavior with reduced resonance effects.
4. The optimized device structure demonstrates improved RF stability, reduced parasitic effects, and superior noise performance, positioning it as a strong candidate for next-generation low-noise microwave, millimeter-wave, and terahertz integrated circuits.

The authors emphasize that these findings are derived from TCAD simulations and highlight the trade-offs between geometric scaling, bias conditions, and noise performance without proposing new experimental fabrication methods or specific commercial applications beyond the general scope of high-frequency electronics.