🔬 physics

Hardware-aware quantum error correction using cryogenic FeFET-weighted Max-SAT decoding

This paper presents a hardware-aware quantum error correction framework that utilizes experimentally characterized cryogenic HZO ferroelectric field-effect transistors to translate measured differential read currents into Max-SAT optimization coefficients, demonstrating that device-level physics can effectively define decoding landscapes while maintaining performance through extensive endurance cycles.

Original authors: Agniva Paul, Apu Das, Ankita Dutta, Debraj Barman, Artur Useinov, Tian-Li Wu, Guilhem Larrieu, Min-Hung Lee, Darsen Lu, Sayani Majumdar, Yannick Raffel, Sourav De

Published 2026-09-01

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Agniva Paul, Apu Das, Ankita Dutta, Debraj Barman, Artur Useinov, Tian-Li Wu, Guilhem Larrieu, Min-Hung Lee, Darsen Lu, Sayani Majumdar, Yannick Raffel, Sourav De

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Quantum computers promise to solve problems that would take today's supercomputers thousands of years to crack, but they are incredibly fragile. The information they hold, known as quantum bits, can easily be scrambled by the slightest heat or electrical noise. To keep these machines working, scientists must constantly check for mistakes and fix them in real time, a process called quantum error correction. This requires a classical computer to act as a guardian, reading the status of the quantum bits, figuring out what went wrong, and sending a correction command back almost instantly. As quantum computers grow larger, the amount of data this guardian needs to process explodes, creating a bottleneck where the correction system itself becomes too slow or too hot to keep up. If the guardian cannot keep pace, the quantum computer fails.

A team of researchers has proposed a way to solve this by moving the guardian closer to the quantum machine and giving it a new kind of memory. Instead of sending vast amounts of data back to a room-temperature computer to be processed, they suggest placing a specialized decoder directly inside the freezing cold environment where the quantum computer lives. To make this work, they turned to a specific type of transistor made from a material called hafnium zirconium oxide, which can store information by changing its electrical state. The researchers tested these devices at a temperature of 10 Kelvin, which is just ten degrees above absolute zero, and found that they could reliably store and read data even in such extreme cold. By measuring the tiny electrical currents flowing through these transistors, they were able to translate the physical behavior of the hardware directly into the mathematical rules needed to fix quantum errors.

The core of the study involved building a system where the decoder does not rely on perfect, theoretical numbers. In traditional approaches, engineers assume their hardware works exactly as designed, ignoring the tiny imperfections that happen in real life. The researchers took a different path. They programmed their transistors to represent different weights, or importance levels, for various possible errors. They then measured the actual electrical current coming out of these transistors after they had been switched on and off many times. This current was used to set the rules for the decoder. If the transistor was healthy, the current was strong and clear. If the transistor had worn out from repeated use, the current changed, and the decoder automatically adjusted its rules to match that new reality. This created a direct link between the physical health of the hardware and the accuracy of the error correction.

The team tested this system by simulating a quantum error correction scenario using a specific code known as the Steane code, which involves seven quantum bits. They ran the decoder using the currents measured from fresh transistors and then compared those results to currents measured after the transistors had been cycled through one hundred thousand program and erase operations. The results showed that as long as the transistors were within their reliable operating range, the decoder performed just as well as if it were using perfect, ideal numbers. The system successfully identified and corrected errors with high accuracy, proving that the physical state of the device could serve as the brain of the correction process without needing complex software to interpret it first.

However, the study also revealed a clear limit to this approach. When the researchers pushed the transistors beyond one million cycles, the material began to degrade significantly. The electrical currents that once clearly distinguished between different states started to blur and overlap. As this happened, the decoder's ability to tell the difference between a correct state and an error collapsed. The logical error rate, which measures how often the system fails to fix a mistake, rose sharply. This demonstrated that the reliability of the quantum error correction is inextricably tied to the lifespan of the memory device itself. The hardware does not just support the calculation; it actively defines how well the calculation works.

This work offers a realistic pathway toward building faster, more efficient quantum computers. By using the actual physical properties of the hardware to drive the decoding process, the system avoids the delays and energy costs of moving data between different temperature zones. The researchers showed that it is possible to build a decoder that lives in the cold, reads its own memory, and corrects errors in real time. While the technology is not yet a finished product, the experiment proves that the bridge between the fragile quantum world and the robust classical world can be built using the very materials that make up the computer. The findings suggest that future quantum machines may not need to fight against the imperfections of their components, but rather learn to work with them, using the physical evolution of the hardware to guide the path to accurate computation.

Technical Summary: Hardware-aware Quantum Error Correction using Cryogenic FeFET-weighted Max-SAT Decoding

Problem Statement
Fault-tolerant quantum computing requires quantum error correction (QEC) to protect information against decoherence and operational errors. As quantum processors scale, the volume of classical syndrome data generated for decoding increases, creating bottlenecks in latency, throughput, and energy efficiency when transferring data to room-temperature electronics. While optimization-based decoders (e.g., Max-SAT) offer a pathway to hardware acceleration by mapping decoding to constrained Boolean optimization, existing hardware-focused studies typically rely on idealized device models or synthetic fault injections. Consequently, the influence of experimentally measured, non-ideal device behavior—specifically the evolution of device states under cryogenic conditions and endurance cycling—remains largely unexplored in the context of QEC performance.

Methodology
The authors propose a device-oriented decoding framework that directly integrates experimentally characterized cryogenic ferroelectric field-effect transistor (FeFET) behavior into a weighted Max-SAT decoding formulation.

Device Platform: The study utilizes Hafnium-Zirconium-Oxide (HZO) based FeFETs operating at 10 K. These devices are programmed into complementary Low-Threshold-Voltage (LVT) and High-Threshold-Voltage (HVT) states using positive and negative voltage pulses.
Differential Encoding: Instead of storing weights digitally, the optimization coefficients are encoded as signed values derived from the differential read current ( $\Delta I = I_{LVT} - I_{HVT}$ ) measured at 10 K. This current difference is mapped to ternary coefficients ( $\{-1, 0, +1\}$ ) representing the coupling strengths in the optimization problem.
Decoding Formulation: The QEC problem for the Steane code is formulated as a weighted Max-SAT problem. Stabilizer relations are enforced as hard constraints (parity checks), while error priors are represented by weighted soft clauses. The objective is to find the error configuration that satisfies all hard constraints while minimizing the penalty of unsatisfied soft clauses. This is mapped to a Quadratic Unconstrained Binary Optimization (QUBO) problem.
Measurement-Anchored Evaluation: Rather than using compact models, the authors extract optimization coefficients directly from measured transfer characteristics of the FeFETs. They evaluate decoder performance under three conditions:
- Freshly programmed devices.
- Devices subjected to $10^5$ program/erase cycles.
- Devices subjected to $10^6$ program/erase cycles.
Benchmarking: The proposed FeFET-weighted Max-SAT decoder is benchmarked against the Minimum-Weight Perfect Matching (MWPM) decoder and ideal numerical weights using identical circuit-level noise realizations (Stim). Statistical validation includes chip-to-chip variability analysis using virtual chips generated from measured current distributions.

Key Results

Cryogenic Characterization: At 10 K, HZO FeFETs exhibit distinct LVT and HVT states. Increasing the program/erase pulse width (from 1 to 50 $\mu$ s) improves the separation of transfer characteristics and the read-current ratio ( $I_{LVT}/I_{HVT}$ ), which increases by nearly two orders of magnitude as the pulse width increases.
Endurance Stability: The devices maintain well-separated states and a stable differential current margin (ratio $\sim 10^4$ ) for approximately $10^5$ program/erase cycles. Beyond this point, approaching $10^6$ cycles, the transfer characteristics begin to overlap and invert, causing the differential current margin to collapse.
Decoding Performance:
- $10^5$ Cycles: The logical error probability using FeFET-derived weights is nearly indistinguishable from that obtained using ideal numerical weights. The decoder performance remains stable across code distances $d=3, 5, 7$ .
- $10^6$ Cycles: As device states invert and current margins collapse, the extracted optimization coefficients deviate significantly, leading to a rapid increase in logical error probability, approaching random decoding outcomes.
Comparison with MWPM: The weighted Max-SAT decoder achieves logical error suppression comparable to the standard MWPM decoder under identical noise conditions, validating the optimization formulation.
Variability: Chip-to-chip variability analysis shows that realistic device-to-device variations have minimal impact on decoding performance as long as the differential current margin remains stable (up to $10^5$ cycles).

Significance and Claims
The paper claims to establish a "measurement-anchored" framework that directly connects cryogenic device physics with optimization-based quantum error correction. Its primary significance lies in demonstrating that:

Device Physics Defines the Optimization Landscape: The reliability of the quantum decoder is intrinsically linked to the physical evolution of the memory device. The study shows that decoder performance tracks experimental device degradation without the need for synthetic perturbation models.
Feasibility of Cryogenic Hardware: Cryogenic FeFETs can serve as viable hardware primitives for QEC decoders, maintaining decoding accuracy comparable to ideal weights for a substantial endurance range ( $10^5$ cycles).
Endurance as a System Metric: Endurance is reframed not just as a memory reliability metric but as a system-level parameter governing computational fidelity in hardware-assisted QEC.
Pathway to Hardware-Assisted Decoders: The work provides a realistic pathway for future hardware-assisted quantum decoders by validating that experimentally measured device states can directly parameterize the decoding process, bridging the gap between emerging non-volatile memory technologies and fault-tolerant quantum computing requirements.

The authors note limitations, including the use of offline decoding rather than a fully integrated cryogenic accelerator, and the restriction to the Steane code and a single FeFET platform, suggesting these as areas for future investigation.

More like this