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Topological-Insulator Heterophase Gate Stacks for Transistor Electrostatics

This paper demonstrates that engineering the gate-side screening boundary by converting the surface of a topological insulator (Bi₂Se₃) into an insulating high-κ layer (BiF₃) creates a reconstructed interface that, despite reducing nominal capacitance, significantly improves transistor electrostatics by enabling near-thermionic switching and drastically lowering drain-induced barrier lowering.

Original authors: Hoon Hahn Yoon, Minuk Song, Jiwan Kim, MD Gius Uddin, Wonseok Kim, Jihun Park, Han Uk Lee, Dong Won Jeon, Dohyung Lee, Lide Yao, Jouko Lahtinen, Gyunghyun Jang, Soohyun Min, Yonas Megra, Xiaoqi Cui, S

Published 2026-09-21

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Hoon Hahn Yoon, Minuk Song, Jiwan Kim, MD Gius Uddin, Wonseok Kim, Jihun Park, Han Uk Lee, Dong Won Jeon, Dohyung Lee, Lide Yao, Jouko Lahtinen, Gyunghyun Jang, Soohyun Min, Yonas Megra, Xiaoqi Cui, Seungwoo Choi, Yunyun Dai, Sang Hoon Chae, Keun Su Kim, Dong-Ho Kang, Hyeon-Jin Shin, Wooseok Song, Seth Tongay, Chul-Ho Lee, Manish Chhowalla, Sung Beom Cho, Zhipei Sun, Kibog Park

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

To make the tiny transistors that power our modern world work faster and use less energy, engineers have spent decades shrinking the layers inside them. One critical layer is the insulator, a thin sheet that sits between the electrical gate and the channel where current flows. The goal has always been to make this insulator as thin as possible while keeping it strong enough to stop electricity from leaking through. However, as these layers approach the thickness of a few atoms, a new problem emerges. The very edge where the metal gate meets the insulator begins to act like a sponge, soaking up some of the electrical control before it can reach the channel. This "sponge effect" at the boundary limits how well the transistor can switch on and off, creating a bottleneck that traditional materials cannot easily fix.

A team of researchers from institutions across South Korea, Finland, the United States, and the United Kingdom has found a way to move this problematic boundary away from the surface and bury it deep inside the material. Instead of trying to perfect the surface where the metal touches the insulator, they engineered a new type of gate stack using a material called bismuth selenide. By treating the surface of this material with a specific gas, they converted the top layer into an insulator while leaving the layer beneath it electrically active. This created a hidden, internal boundary that controls the electricity, effectively bypassing the limitations of the surface. The result is a transistor that switches more cleanly and resists interference from voltage changes much better than previous designs, even though the total electrical capacity of the stack is technically lower.

The researchers started with a flake of bismuth selenide, a material known for its unique electronic properties. They exposed the surface of this flake to a plasma containing sulfur hexafluoride gas. This process chemically transformed the top portion of the material into bismuth fluoride, a robust insulator, while the material underneath remained a conductor. This created a vertical sandwich: an insulating top layer sitting directly on a conducting bottom layer. To confirm this structure, they used powerful microscopes to look at the cross-section of the material. They observed that the conversion stopped naturally at a depth of about 40 to 43 nanometers, leaving a distinct boundary between the insulating top and the conducting bottom. Electrical tests showed that the converted top layer successfully blocked current, while the bottom layer continued to carry electricity, proving that the two states could coexist in a single piece of material.

The most surprising discovery came when the team looked at the electronic behavior right at the interface between the insulating top and the conducting bottom. Using computer simulations, they found that the immediate contact point between the two phases opened up a gap, making it insulating. However, just one atomic layer deeper, inside the conducting material, a new electronic state formed that remained open and active. This hidden layer, buried beneath the insulator, acts as the true gate for the transistor. It is here that the electric field from the gate electrode is screened, or filtered, before it reaches the channel. The researchers measured this buried boundary and found it possessed a specific electronic response that reduced the overall capacitance of the stack. In simpler terms, the system became slightly less efficient at storing charge than a standard insulator would be, which is usually a disadvantage.

Despite this reduction in charge storage, the transistors built with this new architecture performed significantly better than those using a standard insulator. The team built field-effect transistors using molybdenum disulfide as the channel and compared two versions: one with the new buried boundary and one with a standard insulator of the same thickness. The transistor with the buried boundary switched on and off much more sharply, reaching a subthreshold swing of about 65 millivolts per decade, which is very close to the theoretical limit for room-temperature operation. In contrast, the control transistor with the standard insulator required about 83 millivolts to switch. Furthermore, the new design showed almost no hysteresis, meaning the transistor behaved consistently regardless of whether the voltage was being increased or decreased, a common issue in other advanced materials.

Perhaps the most critical improvement was in how the transistor handled changes in drain voltage. In standard transistors, increasing the voltage at the output can inadvertently lower the barrier that keeps the current off, a phenomenon known as drain-induced barrier lowering. The new design reduced this effect by nearly sevenfold, dropping from about 87 millivolts per volt in the control device to just 12 millivolts per volt. This means the new transistor stays firmly off when it should, even when the output voltage fluctuates, making it far more stable and reliable. The researchers also tested a control device where the surface was simply oxidized by air, which created an insulating layer but did not produce the same buried conducting boundary. That device performed poorly, confirming that the specific internal structure created by the fluorination process, rather than just the presence of an insulator, was responsible for the improved performance.

The study demonstrates that the position and electronic nature of the gate-side boundary are just as important as the thickness and material of the insulator itself. By engineering a material that creates a hidden, active boundary deep within the stack, the researchers showed that it is possible to bypass the limitations of surface interactions that have constrained transistor scaling for years. The work suggests that future transistors could be designed not just by making layers thinner, but by rearranging where the electrical control happens. While the new architecture introduces a finite electronic response that lowers the total capacitance, the resulting improvements in switching speed, stability, and resistance to voltage interference offer a compelling new path forward for electronic devices. The findings provide a concrete example of how manipulating the internal structure of a material can solve problems that surface-level engineering cannot.

Technical Summary: Topological-Insulator Heterophase Gate Stacks for Transistor Electrostatics

Problem Statement
Conventional transistor scaling relies on reducing the physical thickness of gate dielectrics and increasing their permittivity to lower the Equivalent Oxide Thickness (EOT). However, as EOT approaches the sub-nanometer regime, the total electrostatic response is increasingly constrained by finite interfacial effects at the gate-electrode/dielectric boundary. These effects—arising from electrode screening, interfacial bonding, polarization, and chemical reconstruction—do not necessarily scale with the bulk dielectric thickness. Consequently, the position and electronic character of the gate-side screening boundary become critical design variables. In two-dimensional (2D) van der Waals (vdW) semiconductors, integrating conventional high-κ dielectrics is particularly challenging due to interfacial disorder and the difficulty of creating a clean, electronically active boundary independent of the semiconductor surface. The central question addressed is whether the gate-side screening boundary can be deliberately engineered, displaced, and reconstructed independently of the semiconductor-channel interface.

Methodology
The authors propose and realize a Topological-Insulator Heterophase Gate Stack (TIHGS) using bismuth selenide (Bi₂Se₃). The core methodology involves the selective surface conversion of the topological insulator Bi₂Se₃ into an insulating, wide-bandgap amorphous bismuth fluoride (BiF₃) phase using SF₆/Ar plasma treatment, while retaining the underlying crystalline Bi₂Se₃ as an electrically conducting layer.

Key experimental and theoretical approaches include:

Material Synthesis & Characterization: Polycrystalline and mechanically exfoliated Bi₂Se₃ films were subjected to controlled plasma fluorination. Structural and chemical properties were verified using cross-sectional Transmission Electron Microscopy (TEM), High-Angle Annular Dark-Field Scanning TEM (HAADF-STEM), Energy-Dispersive X-ray Spectroscopy (EDS), Atomic Force Microscopy (AFM), Raman spectroscopy, and X-ray Photoelectron Spectroscopy (XPS).
Theoretical Modeling: Density Functional Theory (DFT) calculations with spin-orbit coupling were performed to model the electronic structure of the a-BiF₃/c-Bi₂Se₃ heterophase interface. These calculations focused on position-resolved band structures and dipole moments to identify the location of the electronic screening boundary.
Electrical Characterization: Metal-Insulator-Metal (MIM) capacitors and Metal-Insulator-Semiconductor Capacitors (MISCAPs) were fabricated to measure capacitance-voltage (C-V) characteristics and extract effective permittivity and quantum capacitance.
Device Fabrication: MoS₂ Field-Effect Transistors (FETs) were constructed using three distinct gate-stack configurations: (1) TIHGS (partially converted BiF₃/Bi₂Se₃), (2) BiF₃-only (fully converted BiF₃), and (3) an air-oxidized BiOₓ/Bi₂Se₃ control. The TIHGS and BiF₃-only devices were designed with closely matched physical BiF₃ thicknesses (~43 nm) and a common BiF₃/MoS₂ channel-side interface to isolate the effect of the gate-side boundary.

Key Contributions and Results

Creation of a Buried Screening Boundary: The study demonstrates that selective fluorination creates a vertically stratified structure: an insulating amorphous BiF₃ layer on top of a conducting crystalline Bi₂Se₃ layer. This architecture displaces the gate-side electrostatic termination from the external metal/dielectric interface to a "buried" heterophase boundary within the material stack.
Electronic Reconstruction at the Interface: Position-resolved DFT calculations reveal that the immediate a-BiF₃/c-Bi₂Se₃ chemical interface is gap-opened (~0.72 eV). However, an electronically active, gap-closed, Bi₂Se₃-derived Dirac-like state is reconstructed in the adjacent subinterface layer, accompanied by a localized interfacial dipole. This confirms that the electronic screening boundary is spatially separated from the chemical conversion front.
Electrostatic Response and Quantum Capacitance: Capacitor measurements show that the TIHGS stack exhibits a lower effective capacitance than a pure BiF₃ dielectric of the same thickness. This reduction is attributed to a finite series quantum capacitance ( $C_Q$ ) associated with the buried electronic boundary, which acts as an electronically compressible layer. The effective relative permittivity ( $\varepsilon_{eff,TIHGS}$ ) of the TIHGS stack is approximately 15–16, compared to ~28.65 for pure BiF₃.
Enhanced Transistor Performance: Despite the lower nominal stack capacitance, MoS₂ transistors gated by the TIHGS outperform those gated by a pure BiF₃ dielectric. The TIHGS devices exhibit:
- Near-thermionic switching with a minimum subthreshold swing (SS) of ~65 mV dec⁻¹ (compared to ~83 mV dec⁻¹ for the control).
- Negligible hysteresis.
- A significantly suppressed Drain-Induced Barrier Lowering (DIBL) of ~12 mV V⁻¹, compared to ~87 mV V⁻¹ for the BiF₃-only control.
- These improvements are observed despite the TIHGS having a lower capacitance, indicating that the relocated and reconstructed nature of the screening boundary improves electrostatic control.

Significance and Claims
The paper claims that the TIHGS architecture establishes the position and electronic character of the gate-side screening boundary as independent design variables for transistor electrostatics, complementary to conventional high-κ and EOT scaling. By engineering a heterophase material where the chemical interface (gap-opened) and the electronic screening boundary (gap-closed, reconstructed state) are distinct, the authors demonstrate that transistor performance can be optimized not just by thinning the dielectric, but by manipulating the electronic structure of the boundary itself.

The authors modestly note that while the finite quantum capacitance ( $C_Q$ ) is an independent electrostatic signature consistent with an electronically compressible boundary, it is not assigned as the sole causal mechanism for the improved transistor performance. The observed benefits likely arise from a combination of the reconstructed state, interface dipole, and the specific boundary condition, rather than a simple increase in capacitance. The work suggests that future gate-stack design should consider the "buried" electronic boundary as a tunable parameter, offering a new pathway for electrostatic control in advanced semiconductor devices beyond the limits of traditional dielectric scaling.

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