An On-Chip Ultra-wideband Antenna with Area-Bandwidth Optimization for Sub-Terahertz Transceivers and Radars

This paper presents a compact, dual-slot on-chip antenna operating at 290 GHz that achieves a maximum efficiency of 42% and a 39% impedance bandwidth on a low-resistivity silicon substrate, making it suitable for sub-terahertz transceivers and radar applications.

The Gist

Imagine you are trying to build a super-fast wireless internet connection, but instead of using the radio waves your Wi-Fi router uses, you want to use Terahertz waves. These are like "super-high-speed" waves that can carry massive amounts of data, perfect for future 6G networks or ultra-precise radar systems.

However, there's a big problem: these waves are so high-frequency that they get absorbed and lost very easily, especially if you try to put the antenna (the part that sends and receives the signal) directly onto a computer chip. It's like trying to shout across a crowded, noisy room; most of your voice gets lost before it reaches the other side.

Here is a simple breakdown of what the researchers at UCLA did to solve this:

1. The Challenge: The "Tiny, Noisy Room"

The researchers wanted to build an antenna directly onto a silicon chip (the brain of a computer). But silicon chips are made of a material that is naturally "sticky" to these high-frequency waves—it eats them up.

• The Analogy: Imagine trying to bounce a ball on a trampoline made of wet sand. The ball (the signal) just sinks in and stops.
• The Goal: They needed to build a tiny antenna that could shout loud enough to be heard (high efficiency) and talk across a wide range of frequencies (broad bandwidth) without getting lost in the "wet sand" of the silicon chip.

2. The Solution: The "Dual-Slot" Design

Instead of building a traditional antenna, they designed a Dual-Slot Antenna.

• The Analogy: Think of a standard antenna like a solid drum. If you hit it, it makes one specific sound. The researchers instead cut two specific "slots" (openings) into the metal layer of the chip, like cutting two different-sized windows in a wall.
• How it works: These two slots act like a team. One slot handles the lower part of the frequency range, and the other handles the higher part. By working together, they create a "super-chord" that covers a huge range of frequencies (39% bandwidth) without needing a huge antenna.

3. The Optimization: "Fitting a Sofa in a Shoebox"

Usually, to get a wide range of frequencies, you need a big antenna. But on a microchip, space is as valuable as real estate in Manhattan.

• The Analogy: They had to fit a comfortable, wide-coverage sofa into a space the size of a shoebox.
• The Trick: They didn't just make the slots bigger. They added a "director" (a small extra piece of metal) and tweaked the shape of the ground (the base of the antenna). It's like adjusting the legs of a table so it doesn't wobble, even though the table is tiny. They managed to shrink the antenna down to 0.24mm by 0.42mm (smaller than a grain of rice!) while keeping it powerful.

4. The Result: A "Super-Whisper"

When they tested the antenna:

• Efficiency: It managed to keep 42% of the signal from being lost. In the world of tiny chip antennas, this is like getting 42% of your voice to carry across the room without fading away. That is a huge success!
• Speed: It covers a massive range of frequencies, meaning it can handle data streams that are much faster than current technology.
• Size: It is so small it fits perfectly on a single chip, meaning we don't need bulky external antennas for future devices.

Why Does This Matter?

Think of this antenna as the missing link for the next generation of technology.

• For Phones: It could allow your phone to download a whole movie in a split second.
• For Self-Driving Cars: It could act as a super-precise radar that sees through fog and rain better than anything else.
• For Medical Scanners: It could create incredibly detailed images of the human body without using harmful radiation.

In a nutshell: The team figured out how to build a tiny, super-efficient "megaphone" directly onto a computer chip. They used a clever "two-window" design to shout loud and clear across a wide range of frequencies, solving the problem of signals getting lost in silicon. This paves the way for faster internet, smarter cars, and better medical tools in the near future.

Technical Summary

1. Problem Statement

The rapid advancement of sub-Terahertz (sub-THz) systems (frequencies >100 GHz) for high-speed communication and advanced sensing faces significant challenges in antenna integration:

• Integration Constraints: Conventional off-chip antennas are bulky and introduce interconnection losses. On-chip integration is essential for compact, low-cost, and scalable transceivers but is difficult to implement.
• Performance Trade-offs: As antenna size is miniaturized to fit on-chip, maintaining high efficiency, gain, and bandwidth becomes increasingly difficult.
• Process Limitations: Modern CMOS processes (e.g., 16nm FinFET) feature thinner metal layers, which increase Ohmic losses. Furthermore, low-resistivity silicon substrates (typically ~10 S/m) cause significant signal attenuation and loss of radiation efficiency.
• Design Complexity: Achieving a wide impedance bandwidth (necessary for wideband transceivers) while keeping the physical footprint small and maintaining directivity (>5 dBi) in a single-layer structure is a major engineering hurdle.

2. Methodology

The authors propose a single-layer, dual-slot antenna designed in 16nm FinFET technology (TSMC N16HPC process) to address these challenges.

• Substrate and Material Strategy:

  • The antenna is constructed in the thickest available high-conductivity metal layer (M9) to minimize resistive losses.
  • Lower metal layers (M1–M8) are filled with dummy metal to satisfy foundry density rules. To reduce computational cost during simulation, these dummy layers are modeled as an artificial dielectric layer using an effective wave number approximation.
  • The design utilizes a Co-planar Waveguide (CPW) feed to ensure a well-defined current return path and facilitate seamless integration with on-chip circuits.

• Design Evolution (Four Stages):

  1. Stage 1 (Baseline): A simple slot dipole with a large ground plane to establish baseline radiation efficiency and impedance matching.
  2. Stage 2 (Directivity Enhancement): Introduction of a director element to improve directivity and gain without increasing the footprint. This creates a second resonance, broadening the bandwidth.
  3. Stage 3 (Area Optimization): The ground plane size is reduced, and the director is partially opened. This shifts the second resonance to higher frequencies to enhance bandwidth while minimizing the silicon footprint.
  4. Stage 4 (Impedance Matching): A square tuning element is added to bridge the impedance gap between the two resonances. This element acts as a coupling mechanism to smooth the impedance curve across the target frequency range.

3. Key Contributions

• Dual-Slot Architecture: A novel dual-slot structure that effectively balances area constraints with the need for wide bandwidth and high directivity on a lossy substrate.
• Area-Bandwidth Optimization: The design achieves a compact footprint of 0.24λ₀ × 0.42λ₀ while maintaining a wide impedance bandwidth, addressing the critical trade-off between miniaturization and performance.
• High Efficiency on Low-Resistivity Silicon: By optimizing the metal stack and utilizing the thickest metal layer, the design overcomes the typical efficiency penalties associated with low-resistivity silicon substrates.
• Comprehensive Validation: The work includes rigorous simulation modeling of dummy metal fills and experimental validation using an on-chip transmitter and a far-field measurement setup.

4. Results

• Performance Metrics:
  • Center Frequency: 290 GHz.
  • Impedance Bandwidth: 39% (covering a range of approximately 114 GHz).
  • Peak Radiation Efficiency: 42% (measured at ~275 GHz).
  • Directivity: 7.0 dBi at 290 GHz.
  • Physical Dimensions: 0.24 mm × 0.42 mm (0.10 mm²).
• Measurement Setup: The antenna was integrated with an on-chip transmitter (up-converting a CW signal via multipliers) and tested in a far-field setup using a standard-gain horn antenna (25 dBi) and a spectrum analyzer.
• Comparison: As shown in Table III of the paper, this work outperforms several state-of-the-art on-chip antennas (using InP, SiGe, and other CMOS technologies) in terms of bandwidth (39% vs. 3.6%–26.2%) and area efficiency, while achieving competitive directivity.

5. Significance

This research provides a critical enabler for the next generation of sub-THz integrated transceivers and radar systems.

• System Integration: The compact, single-layer design allows for seamless integration with sub-THz circuits, reducing system size, cost, and interconnection losses.
• Practical Viability: By demonstrating high efficiency (42%) on standard low-resistivity silicon, the work proves that high-performance sub-THz antennas can be fabricated using standard CMOS processes without exotic materials or complex 3D packaging.
• Application Impact: The wide bandwidth and high directivity make this antenna suitable for high-data-rate wireless communications (6G and beyond) and high-resolution imaging/radar applications.