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Characterization of a 28 nm $\textit{smartpixels}$ ASIC With On-Chip ML for Particle Tracking Detectors

This paper presents the characterization of a 28 nm CMOS ASIC for particle tracking detectors that integrates in-pixel analog signal processing and an on-chip neural network classifier to achieve low noise, high linearity, and effective data reduction with 99.06% agreement between hardware measurements and offline predictions.

Original authors: Benjamin Parpillon, Anthony Badea, Danush Shekar, Cristian Gingu, Giuseppe Di Guglielmo, Tom Deline, Sergey Los, Adam Quinn, Michele Ronchi, Daniel Abadjiev, Doug Berry, Arghya Ranjan Das, Jennet Dick

Published 2026-08-18

📖 6 min read🧠 Deep dive

CC BY 4.0

Original authors: Benjamin Parpillon, Anthony Badea, Danush Shekar, Cristian Gingu, Giuseppe Di Guglielmo, Tom Deline, Sergey Los, Adam Quinn, Michele Ronchi, Daniel Abadjiev, Doug Berry, Arghya Ranjan Das, Jennet Dickinson, Karri DiPetrillo, Farah Fahim, Lindsey Gray, Harshul Gupta, Eliza Howard, David Jiang, Pamela Klabbers, Mira Littmann, Mia Liu, Petar Maksimovic, Nick Manganelli, Corrinne Mills, Mark S. Neubauer, Jannicke Pearkes, Paul Rubinov, Ricardo Silvestre, Morris Swartz, Chinar Syal, Nhan Tran, Amit Trivedi, Keith Ulmer, Mohammad Abrar Wadud, Benjamin Weiss, Jieun Yoo, Eric You

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

In the heart of modern physics, scientists are building machines to smash particles together at speeds approaching the speed of light, hoping to uncover the fundamental rules that govern our universe. These collisions happen billions of times every second, creating a chaotic storm of subatomic debris that must be captured and analyzed. To do this, researchers use detectors made of silicon, similar to the chips in a smartphone but far more sensitive. These detectors act like a grid of tiny eyes, each one watching for a flash of energy when a particle passes through. However, the sheer volume of data generated by these collisions is becoming impossible to manage. If every single flash were sent to a computer for analysis, the communication lines would clog, and the most important signals would be lost in the noise. The challenge is not just to see the particles, but to decide instantly which ones are worth keeping and which ones are just background static, all before the data leaves the detector itself.

To solve this problem, a team of researchers has built a new type of computer chip that can think for itself right at the point of detection. This chip, known as a smart pixel, is designed to not only sense the passage of a particle but also to analyze the shape of the energy it leaves behind and make a split-second decision on whether to keep the data. The researchers created a prototype using a very advanced manufacturing process, shrinking the electronic components down to a size of 28 nanometers, which is roughly one-thousandth the width of a human hair. On this tiny chip, they arranged two large grids of microscopic sensors, each grid containing hundreds of individual pixels. Every single pixel is a self-contained laboratory, equipped with its own amplifier to boost the faint signal from a passing particle and a digital converter to turn that signal into a number.

What makes this chip truly unique is that it does not just record the raw data; it processes it immediately. In traditional detectors, the chip simply counts how much energy was deposited and sends that number away. Here, the chip takes the raw signal, converts it into a few digital bits, and then feeds those bits into a small, built-in brain—a neural network. This neural network is a type of artificial intelligence that has been taught to recognize patterns. It looks at the cluster of energy left by a particle and decides if that particle is likely to be interesting for scientific study or if it is just random noise. By making this decision inside the chip, the system can discard the vast majority of useless data before it ever leaves the detector, freeing up bandwidth for the truly important events.

The researchers tested this chip by simulating the arrival of particles using precise electrical pulses. They wanted to see if the chip could handle the noise and speed required for future experiments, specifically those planned for the High-Luminosity Large Hadron Collider, a massive particle accelerator that will soon be upgraded to produce even more collisions than ever before. The tests showed that the chip works remarkably well. When they measured the noise level of the sensors, they found it was extremely low, allowing the chip to detect very faint signals without being confused by static. The digital brain inside the chip proved to be incredibly reliable, matching the predictions of computer simulations with an accuracy of over 99 percent. This means that the chip is making the same decisions a powerful computer would make, but it does so in a fraction of a second and using a tiny amount of energy.

One of the most impressive aspects of the design is how efficiently it uses power. The chip was tested at a speed of 10 million cycles per second, and even with the added task of running a neural network, it consumed very little electricity. The researchers calculated that if the chip were to run at the full speed of 40 million cycles per second, which is the target for future detectors, the total power usage would still fit within the strict limits required for these massive experiments. This is crucial because the detectors are packed so tightly that they cannot afford to overheat or drain too much power. The chip also demonstrated that it could handle different types of electrical signals, showing that the design is robust enough to be adapted for various conditions.

However, the researchers were careful to note that this was a first version of the chip, and like any prototype, it had some imperfections. They discovered that the way the chip was calibrated caused some small errors in how it measured the energy of particles, particularly when many pixels were active at the same time. They also found that the chip's ability to distinguish between very low levels of energy could be improved with a few design tweaks. These are not fundamental flaws in the idea of a smart chip, but rather growing pains of a new technology. The team has already outlined how they will fix these issues in the next version, such as by giving each pixel its own dedicated calibration line to avoid interference.

The success of this prototype marks a significant step forward in the quest to build smarter detectors. It proves that it is possible to put complex decision-making tools directly onto the silicon sensors that watch the universe. By filtering out the noise at the very source, these chips could allow scientists to see deeper into the collisions, capturing rare and fleeting events that would otherwise be buried in a sea of data. The work presented here does not just show that the technology works; it shows that it works with the precision and efficiency needed for the next generation of discovery. As the team moves toward building the final version, they are confident that they can refine the design to handle the extreme conditions of the future particle accelerators, ensuring that the most important signals from the edge of the universe are never lost.

Technical Summary: Characterization of a 28 nm Smartpixels ASIC With On-Chip ML for Particle Tracking Detectors

Problem Statement
Modern silicon pixel detectors for the High-Luminosity Large Hadron Collider (HL-LHC) face unprecedented particle occupancies, generating data rates that exceed the bandwidth available for off-detector transmission. While sensor technology advances, the volume of data places increasing pressure on readout architectures, power consumption, and trigger systems. Conventional readout ASICs perform limited local processing (amplification, discrimination, zero suppression) but treat all surviving hits equally, failing to exploit the rich spatial information within charge clusters to distinguish signal from background. Consequently, a significant fraction of transmitted data contributes little to physics analysis while consuming valuable bandwidth. The challenge is to reduce data volume at the point of acquisition while preserving the physics information necessary for reconstruction, specifically by moving advanced processing closer to the sensor.

Methodology
The authors present the design and first-silicon characterization of a 28 nm CMOS pixel readout integrated circuit (ASIC) that integrates in-pixel analog signal processing with on-chip machine learning (ML) data filtering. The device, referred to as "smartpixels," features two 32×8 pixel matrices (superpixels) with a 25×25 µm² pitch.

Analog Front-End (AFE): Each pixel integrates a charge-sensitive amplifier (CSA) with synchronous auto-zero offset cancellation and a 2-bit flash analog-to-digital converter (ADC). The architecture utilizes bunch-synchronous digitization, where all pixels are sampled using a common temporal reference (bunch-crossing clock), preserving the spatial charge distribution and temporal correlations. Two AFE variants were fabricated and compared: a differential architecture (SP1) and a single-ended architecture (SP2).
Digital Processing: Digitized pixel data are combined into row-wise projections (16 buses of 6-bit values) and processed by a fully combinational neural network (NN) classifier. The NN is designed to classify charge clusters based on the transverse momentum ( $p_T$ ) of incident charged particles. The use of combinational logic minimizes inference latency (completed within a single bunch-crossing period) and reduces dynamic power consumption, as power is only drawn when input patterns change.
Testing Setup: The ASIC was characterized using a charge-injection method via a programmable on-chip capacitor, emulating sensor signals without bump-bonding to a physical sensor. Measurements were conducted at room temperature with a 10 MHz bunch-crossing clock (limited by the test board bandwidth), using a DAQ system based on the Caribou and Spacely frameworks.

Key Contributions and Results
The paper provides a comprehensive characterization of the mixed-signal signal chain, from analog amplification to digital classification:

Analog Performance:
- Noise and Gain: At the optimal bias current (3.15 µA/pixel for the differential SP1 variant), the ASIC achieved an Equivalent Noise Charge (ENC) of 54.6 $e^-$ and a conversion gain of ~57.7 µV/ $e^-$ . These values closely match circuit simulations for the front end without an attached sensor.
- Linearity and Dynamic Range: The system demonstrated a linear response up to several thousand electrons ( $ke^-$ ). A nonlinearity was observed at low thresholds (<400 $e^-$ ) due to charge injection from the comparator sampling switch, and saturation occurred above ~8000 $e^-$ .
- Threshold Dispersion: The measured threshold dispersion was ~~78.2 $e^-$ . The authors attribute the excess over the simulated mismatch limit (~~45 $e^-$ ) to implementation-specific issues, including finite DC input currents in the SP2 threshold interface affecting the shared bias network and distributed RC loading during simultaneous charge injection.
- Power: At 10 MHz, the AFE dissipates ~2.8 µW/pixel.
Digital and NN Performance:
- Power: The on-chip NN logic consumed an average of 0.76 µW/pixel under cluster rates representative of HL-LHC occupancy, consistent with the sparse switching activity of combinational logic.
- RTL-to-Silicon Agreement: The on-chip NN output was compared against offline RTL simulations using 1.5 × 10⁵ test inputs. For discriminator thresholds of ~1000 $e^-$ and above, the agreement reached 99.06%, confirming deterministic operation of the digital logic. A confusion matrix at 1000 $e^-$ showed strong diagonal alignment, indicating bit-accurate classification.
Limitations Identified:
- The prototype utilized a shared global injection line, which caused aggregate capacitive loading and distorted pulse shapes, artificially inflating ENC and threshold dispersion measurements.
- The SP2 single-ended variant exhibited higher threshold dispersion than SP1 due to reduced common-mode rejection and specific DC loading issues.
- Measurements were limited to 10 MHz; operation at the nominal 40 MHz requires further validation of bias currents and settling times.

Significance and Outlook
The paper claims that this work establishes the feasibility of implementing a fully integrated, mixed-signal pixel readout architecture that performs real-time data reduction using on-chip neural networks. The prototype successfully demonstrated end-to-end operation, validating the intrinsic noise performance of the analog front end and the deterministic behavior of the digital classifier.

The authors emphasize that while the current results are promising, they represent a first-silicon prototype with specific implementation limitations. The measured performance validates the underlying architecture but highlights the need for design iterations to address calibration network loading, low-threshold linearity, and threshold bias distribution. Future work will focus on:

Modifying the next prototype to include local in-pixel charge injection and improved threshold biasing.
Validating operation at the nominal 40 MHz bunch-crossing frequency and at lower temperatures (down to -30°C).
Investigating noise-aware retraining of the neural network to recover classification performance at lower thresholds, which is critical for operation after radiation damage.

The paper concludes that these hardware and algorithmic developments provide a path toward reliable intelligent data filtering at the target 400 $e^-$ operating threshold and 40 MHz rate, essential for future high-luminosity particle physics experiments.

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