🔬 applied physics

2D Canonical Approach for Beating the Boltzmann Tyranny Using Memory

This paper presents a universal theoretical framework demonstrating that intrinsic memory effects in nanometric field-effect transistors, modeled via Landauer-Büttiker formalism with dynamic charge trapping, can naturally bypass the 60 mV/decade Boltzmann limit to enable ultra-low-power switching without relying on complex material-specific mechanisms.

Original authors: Rafael Schio Wengenroth Silva, Soumen Pradhan, Fabian Hartmann, Leonardo K. Castelano, Ovidiu Lipan, Sven Höfling, Victor Lopez-Richard

Published 2026-05-19

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CC BY 4.0

Original authors: Rafael Schio Wengenroth Silva, Soumen Pradhan, Fabian Hartmann, Leonardo K. Castelano, Ovidiu Lipan, Sven Höfling, Victor Lopez-Richard

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

The Big Problem: The "60-Millivolt Wall"

Imagine you are trying to turn on a light switch, but the switch is stuck. No matter how hard you push, it takes a lot of effort to get the light to turn on fully.

In the world of computer chips, this "effort" is called voltage. For decades, engineers have hit a fundamental wall known as the "Boltzmann tyranny." It's a rule of physics that says, at room temperature, a transistor (the tiny switch inside your computer) needs at least 60 millivolts of voltage change to switch from "off" to "on" efficiently.

If you try to use less voltage than that, the switch leaks electricity, gets hot, and wastes energy. This is the main reason why our phones and computers can't get much smaller or more energy-efficient without running out of battery or overheating.

The Old Solutions: Heavy Machinery

Scientists have tried to break this wall before. Some tried using special "ferroelectric" materials (like a magnetic memory that remembers its state) to boost the voltage. Think of this like trying to break a wall by bringing in a giant hydraulic press. It works, but it's heavy, complicated to build, and hard to control.

The New Idea: The "Smart Memory" Switch

This paper proposes a different, lighter way to break the wall. Instead of using heavy, special materials, the authors suggest using memory built right into the flow of electricity.

They call these devices "memtransistors."

The Analogy: The Crowded Hallway

Imagine a hallway (the transistor channel) where people (electrons) are trying to run from one end to the other.

The Gate: A person standing at the door with a megaphone (the gate voltage) telling people to run faster.
The Old Way: The megaphone just shouts louder. But physics says there's a limit to how fast the people can react to the shouting.
The New Way (Memory): Imagine that as people run through the hallway, they leave sticky notes on the walls. These sticky notes are trapped charges.
- When the gate shouts, it doesn't just push people; it also changes how many sticky notes are on the wall.
- These sticky notes change the shape of the hallway itself, making it easier for the next group of people to run through.
- Crucially, the sticky notes don't disappear instantly. They linger for a moment, creating a "memory" of the previous shout.

How It Breaks the Limit

The paper uses a mathematical framework (called Landauer–Büttiker) to show that if you manage these sticky notes (the trapped charges) correctly, you can trick the system.

The Dynamic Shift: As you change the gate voltage, the "sticky notes" (trapped charges) appear or disappear. This dynamically reshapes the energy landscape of the transistor.
The Sweet Spot: The authors found a specific condition where the rate at which these charges appear or disappear actually helps the switch turn on faster than the 60mV limit allows.
The Result: Instead of needing a slow, gradual push to turn the switch on, the "memory effect" creates a sudden, steep jump. The switch goes from "off" to "on" with much less voltage change.

The Key Discovery

The paper provides a clear formula showing that if the "generation rate" of these trapped charges changes in a specific way as you adjust the gate, the transistor can achieve sub-thermal switching.

In plain English: The internal memory of the device amplifies the gate's signal. It's like having a lever that multiplies your strength. You push a little bit (low voltage), and the memory mechanism does the heavy lifting, allowing the switch to flip instantly.

Why This Matters (According to the Paper)

No Heavy Machinery: You don't need complex ferroelectric materials. You just need to engineer the "memory" (charge trapping) into standard nanometric transistors.
Universal Rule: This isn't tied to one specific material (like a specific type of metal or crystal). It's a general principle that could apply to many different types of electronic devices.
Energy Efficiency: By breaking the 60mV limit, these devices could run on much less power, leading to computers that are faster and don't get as hot.

Summary

The paper argues that by treating the transistor not just as a static switch, but as a device with a short-term memory (where past electrical states influence the present), we can bypass the fundamental physics limit that has held back computer technology for decades. It's like realizing that if you leave a trail of breadcrumbs, the next person can follow them much faster than if they had to find their own way every time.

Technical Summary: 2D Canonical Approach for Beating the Boltzmann Tyranny Using Memory

Problem Statement
The continued down-scaling of conventional transistors faces a fundamental thermodynamic barrier known as the "Boltzmann tyranny." This phenomenon imposes a minimum subthreshold swing (SS) of approximately 60 mV/decade at room temperature, arising from the Boltzmann tail of Fermi-Dirac statistics governing carrier injection via thermionic emission. Overcoming this limit is critical for reducing supply voltages, scaling device dimensions, and sustaining energy-efficient computing. While various strategies have been proposed—such as tunneling FETs, cold-source FETs, and negative-capacitance FETs utilizing ferroelectric materials—many rely on complex material-specific mechanisms, suffer from leakage issues, or require intricate fabrication and stability controls. Furthermore, a comprehensive quantum transport framework that integrates intrinsic memory mechanisms to bypass this limit has been lacking.

Methodology
The authors develop a universal theoretical framework based on the Landauer–Büttiker quantum transport formalism to model a 2D nanometric field-effect transistor.

Baseline Model: The study begins with a standard description of a 2D diffusive channel under a parabolic band approximation. The current is derived by integrating the difference between source and drain Fermi–Dirac distributions over the energy window defined by the bias voltage.
Incorporation of Memory: To account for history-dependent effects, the model introduces a non-equilibrium variation in trapped charge density ( $\delta n$ ) at the gate interface or within a floating gate. This dynamic charge component renormalizes the conduction band edge ( $E_c$ ), effectively altering the channel electrostatics in real-time.
Dynamics: The evolution of the trapped charge is described by a relaxation-time approximation, governed by a generation function $g(V_g, V_{ds})$ that accounts for carrier trapping and release. This function is generalized to include dependencies on both gate and drain voltages, characterized by efficiency factors and symmetry parameters.
Analytical Derivation: By assuming a separation of timescales where the memory relaxation time is significantly longer than the carrier transit time, the authors derive a quasi-static limit. They substitute the renormalized conduction band edge into the expression for subthreshold swing to obtain an analytical formula linking memory dynamics to gate efficiency.

Key Contributions and Results

Analytical Expression for Subthreshold Swing: The central result is an analytical expression for the subthreshold swing (SS):
$SS = \frac{k_B T \ln(10)}{e} \frac{1}{\eta_g - \beta \tau_m \frac{dg}{dV_g}}$
where $\eta_g$ is the capacitive gate-coupling efficiency, $\beta$ is the coupling factor for trapped charge, $\tau_m$ is the memory relaxation time, and $\frac{dg}{dV_g}$ is the derivative of the carrier generation function with respect to the gate voltage.
Mechanism for Sub-Thermal Switching: The model demonstrates that the term $\beta \tau_m \frac{dg}{dV_g}$ provides an additional, tunable degree of gate control independent of material-specific ferroelectric responses. Specifically, when $\frac{dg}{dV_g} < 0$ near the threshold voltage, the denominator increases, driving the SS below the 60 mV/decade Boltzmann limit. This condition corresponds to scenarios where the carrier generation rate decays with increasing gate voltage (e.g., due to saturation or recombination) or where trapping intensifies.
Hysteresis and I-V Characteristics: The framework successfully reproduces pinched hysteretic I-V loops characteristic of memristive responses under triangular voltage sweeps, as well as the transition from linear to saturation regimes.
Universality: Unlike previous approaches that rely on negative capacitance or specific ferroelectric phase transitions, this mechanism relies on intrinsic nonequilibrium charge dynamics (trapping and release). The model shows that these effects can replicate steep-slope behavior without requiring complex material engineering.

Significance and Claims
The paper claims to establish "memory-assisted transistors" (memtransistors) as a robust pathway toward ultra-low-power and multifunctional electronic architectures. By explicitly coupling nonequilibrium charge-trapping dynamics to quantum transport, the authors provide a general physical principle that allows the Boltzmann limit to be surpassed without relying on ferroelectric materials.

The significance of this work lies in its provision of clear, generalizable design principles. It suggests that engineering intrinsic memory effects—specifically the dynamic balance between carrier generation and trapping—can serve as a built-in functionality to achieve sub-thermal switching. The authors posit that this approach offers a simpler and more controllable route to steep-slope behavior compared to existing strategies, making it broadly applicable across various device platforms for next-generation low-power electronics. The model captures key experimental features observed in nanoscale memtransistors, validating the theoretical framework against known phenomena while offering a new perspective on overcoming thermodynamic limits in semiconductor scaling.