💻 computer science

ADSEQ: A delay-aware autograd-compatible framework for spike-event delivery in SNNs

This paper introduces ADSEQ, a memory-efficient, autograd-compatible framework that enables exact gradient-based training of Spiking Neural Networks with delays by utilizing spike event queues, while demonstrating that optimal queue implementation strategies vary significantly across CPU, GPU, TPU, and LPU hardware platforms.

Original authors: Lennart P. L. Landsmeer, Amirreza Movahedin, Said Hamdioui, Christos Strydis

Published 2026-07-08

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Lennart P. L. Landsmeer, Amirreza Movahedin, Said Hamdioui, Christos Strydis

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to organize a massive, chaotic party where thousands of guests (neurons) are constantly sending each other notes (spikes). The catch? These notes don't arrive instantly. Some take a few seconds, others take a few minutes, and the time it takes varies wildly depending on who is sending the note and how far they have to travel.

This is the problem scientists face when simulating Spiking Neural Networks (SNNs)—computer models that try to mimic how our brains work. To train these models (teach them to learn), the computer needs to know exactly how changing the "delivery time" of a note affects the final result. This is called calculating a gradient.

The paper introduces a new tool called ADSEQ to solve the headache of managing these delayed notes while keeping the math solvable for computers.

Here is the breakdown of what they did, using simple analogies:

1. The Problem: The "Lost in Translation" Delivery

In the past, computers simulated these brain networks in two main ways, both of which had flaws:

The "Smoothie" Approach: To make the math easy, some simulators turned the sharp, sudden "notes" into a smooth, continuous stream of liquid. This made the math work, but it destroyed the efficiency. It's like trying to count individual raindrops by measuring the total volume of a puddle; you lose the specific timing information that makes the system efficient.
The "Rigid Box" Approach: Other simulators used specific, simple boxes (like a ring buffer) to hold the notes. These were fast but couldn't handle complex delays or different types of neurons. They were like a conveyor belt that only works if every package arrives exactly 5 seconds after the last one.

The Gap: No one had a system that could handle complex, variable delays (some notes take 2ms, others 50ms) while still allowing the computer to learn from mistakes (calculate gradients) efficiently.

2. The Solution: ADSEQ (The Smart Courier Service)

The authors built ADSEQ (AutoDifferentiable Spike-Event Queues). Think of this as a super-smart courier service that can handle any type of package, any delivery time, and still keep a perfect receipt for the accountant (the gradient calculator).

The Magic Trick (Custom Gradients): Usually, if you put a package in a box and take it out later, the computer forgets exactly when it went in. ADSEQ uses a special "magic receipt" (mathematical derivatives) that travels inside the package. Even if the package sits in a queue for a long time, the receipt remembers exactly how the delay time affects the final outcome. This allows the computer to learn how to adjust delivery times to make the network smarter.
The Queue: They built a toolbox of different "waiting rooms" (queues) for these notes. Some are simple lines (FIFO), some are priority lists (Heaps), and some are circular tracks (Ring Buffers).

3. The Race: Which Waiting Room is Best?

The authors tested these different waiting rooms on four different types of "super-computers" (AI accelerators) to see which one was the fastest. It turns out, one size does not fit all.

The CPU (The Classic Office Worker):
- Best Queue: Tree-based or FIFO lines.
- Why: The CPU is good at following instructions one by one. It likes organized lines where it can check items off a list.
The GPU (The Super-Parallel Factory):
- Best Queue: Ring Buffers (for small jobs) or FIFO (for huge jobs).
- Why: GPUs are like factories with thousands of workers doing the same task at once. They love circular tracks where everyone moves in sync. However, if the factory gets too crowded, a simple line (FIFO) works better to avoid traffic jams.
The TPU (The Specialized Sorting Machine):
- Best Queue: Sorted Arrays.
- Why: The TPU has a special "sorting machine" built right into its hardware. It doesn't matter how messy the pile of notes is; the TPU can sort them instantly. So, the best strategy is just to dump them in a pile and let the machine sort them.
The LPU (The Deterministic Train):
- Best Queue: Deterministic Dataflow.
- Why: This computer runs like a train on a fixed track. It hates surprises or branching paths. It needs a schedule where every note arrives at a predictable time.

4. The "Drop the Package" Option

Sometimes, the waiting room gets too full. The authors showed that you can program the system to drop some notes if the queue is full.

The Trade-off: Dropping notes makes the simulation run much faster (less memory used), but it's slightly less accurate. It's like a busy post office throwing away letters when the bins are full to keep the line moving. The paper shows you can tune this: drop a few to save speed, or keep them all for perfect accuracy.

Summary

The paper doesn't just say "we made a faster brain simulator." It says: "We built a flexible toolkit (ADSEQ) that lets computers learn from delayed signals, and we proved that the best way to organize these signals depends entirely on the type of computer chip you are using."

If you have a standard computer, use a line.
If you have a graphics card, use a circle or a line.
If you have a Google TPU, use a sorting pile.

This allows scientists to build more realistic brain models and train AI faster, without getting stuck in the math of "when did that signal arrive?"

Technical Summary: ADSEQ – A Delay-Aware Autograd-Compatible Framework for Spike-Event Delivery in SNNs

Problem Statement
Efficient simulation and gradient-based training of Spiking Neural Networks (SNNs) and brain models require handling sparse spike transmission, particularly when incorporating heterogeneous synaptic delays. Current approaches face a dichotomy:

Memory Inefficiency: Machine Learning (ML) library-based simulators often rely on surrogate gradients (e.g., SuperSpike) to handle spike discontinuities. While effective for simplified models, surrogate gradients convert sparse spike events into dense, continuous-time signals. When delays are introduced, these dense signals must be buffered, negating the sparsity benefits and creating memory bottlenecks.
Lack of Generalization: Existing exact-gradient methods (e.g., EventProp) are largely restricted to simplified neuron models (like Leaky Integrate-and-Fire) and specific parameter sets. They often fail to generalize to biophysically realistic models or arbitrary queue structures required for full-brain simulations.
Hardware Mismatch: There is a lack of understanding regarding which spike-event queue data structures (e.g., ring buffers, heaps, FIFOs) perform optimally across diverse AI accelerator architectures (von Neumann CPUs, GPUs, TPUs, and deterministic dataflow LPUs), especially when combined with differentiable operations.

Methodology
The authors introduce ADSEQ (AutoDifferentiable Spike-Event Queues), a framework designed to enable exact, delay-aware gradient calculation within modern ML libraries (specifically JAX).

Mathematical Formulation: The core contribution is the derivation of implicit derivatives for spike-event delivery. By applying the Implicit Function Theorem to the spike detection condition ( $v_{pre}(t_{pre}) = v_{th}$ $v_{p r e} (t_{p r e}) = v_{t h}$ ), the authors derive the gradient of the spike time with respect to model parameters ( $\theta$ $θ$ ) and synaptic delays ( $d$ $d$ ).
- They generalize the EventProp equations to include delay gradients: $dt_{post}/d\theta = dt_{pre}/d\theta + dd/d\theta$ .
- They derive the gradient update for postsynaptic state variables ( $x$ ) upon spike arrival, accounting for the delay: $\partial x^+/\partial \theta = \partial x^-/\partial \theta + (1/\tau) \cdot \partial t_{post}/\partial \theta$ .
Implementation via Custom Gradients: To integrate these derivations into JAX's automatic differentiation (autograd) system, the authors implement custom Jacobian-Vector Product (JVP) operators. These custom gradients are injected into the enqueue() and pop() operations of various queue data structures. This allows the autograd engine to correctly propagate gradients through the time-delayed spike events without requiring manual backpropagation derivations for complex neuron models (e.g., Hodgkin-Huxley).
Queue Variants: The framework implements a suite of differentiable queue structures, including:
- Ring Buffers: Standard and lossy variants (summing spikes or dropping them).
- FIFO Structures: First-In-First-Out queues with capacity limits.
- Tree/Heap Structures: Binary heaps and tournament trees for handling heterogeneous delays.
- Sorted Arrays: Arrays that maintain order via sorting operations.
- Bit-level Structures: Optimized for single-spike scenarios.
Lossy Mechanisms: The framework includes "lossy" queue implementations that deliberately drop spikes when capacity is exceeded, allowing for a tunable performance-accuracy trade-off.

Key Contributions

Autodifferentiable Formulation: A generalized mathematical formulation for exact spike-event gradients that supports both neural parameters and synaptic delays, compatible with arbitrary neuron models.
ADSEQ Library: A collection of differentiable queue data structures implemented in JAX with custom gradients, enabling the use of sparse spike storage in gradient-based training.
Cross-Accelerator Benchmarking: A comprehensive evaluation of these queue structures across four distinct hardware architectures:
- CPU (Intel i7): Von Neumann architecture.
- GPU (NVIDIA H100): Parallel processing with coalesced memory access.
- TPU (Google TPU v4): Tensor and Sparse Cores with dedicated sorting units.
- LPU (Groq LPU): Deterministic dataflow architecture with no control flow branching.
Spike Drop Analysis: Quantification of spike-drop rates for lossy queues, providing data for designing simulators with controllable accuracy constraints.

Results
The benchmarking results reveal that the optimal queue structure is highly dependent on the hardware architecture and workload characteristics:

CPU: Tree-based (Binary Heap) and FIFO-based queues perform best, likely due to lower overhead and efficient handling of conditional logic in von Neumann architectures.
GPU: Ring buffers excel for smaller networks and workloads that fit within cache. However, for larger networks, FIFO structures scale more favorably due to reduced memory pressure.
TPU: Sort-based implementations (Sorted Arrays) significantly outperform other methods. This is attributed to the TPU's dedicated Sparse Cores, which contain hardware-accelerated sorting units.
LPU: Deterministic dataflow scheduling favors structures that avoid divergent control flow.
Scaling: As the number of queues increases, CPU performance degrades rapidly compared to accelerators. However, for small-scale simulations where data fits in local caches, CPUs remain competitive.
Training vs. Inference: Training (parameter tuning) is significantly more computationally and memory-intensive than inference. Forward AD is notably slower than reverse AD in certain configurations, suggesting a need for hybrid methods like checkpointing.

Significance and Claims
The paper claims that ADSEQ establishes a foundation for scalable, reusable components for autograd-compatible SNN simulations that include delays, applicable to both artificial and biologically realistic networks.

Generalization: Unlike previous exact-gradient methods limited to LIF models, ADSEQ supports complex biophysical models (e.g., Hodgkin-Huxley) by treating the queue as a differentiable primitive.
Hardware Awareness: The work demonstrates that "one-size-fits-all" queue strategies are suboptimal. The choice of data structure must align with the underlying accelerator's architecture (e.g., using sort-based structures for TPUs and heaps for CPUs).
Future Integration: The authors suggest that their approach could allow traditional brain simulators (which currently lack gradient support) to incorporate network-level gradients by modifying neuron models to send float-encoded gradient messages alongside spikes, bridging the gap between traditional neuroscience simulators and modern ML frameworks.

The paper concludes that while ML libraries often neglect traditional data structures like FIFOs and trees in favor of simplified arrays, these structures hold significant merit for specific hardware and delay-constrained scenarios, offering a path toward more efficient and realistic SNN training.