⚡ electrical engineering

Low-Complexity Planar Beyond-Diagonal RIS Architecture Design Using Graph Theory

This paper employs graph theory to identify and characterize planar-connected Beyond-Diagonal RIS architectures that can be fabricated on double-layer PCBs while maximizing degrees of freedom to balance performance with reduced circuit complexity.

Original authors: Matteo Nerini, Zheyu Wu, Shanpu Shen, Bruno Clerckx

Published 2026-05-04

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CC BY 4.0

Original authors: Matteo Nerini, Zheyu Wu, Shanpu Shen, Bruno Clerckx

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to organize a massive party where everyone needs to talk to everyone else without shouting over each other. In the world of 6G wireless networks, Reconfigurable Intelligent Surfaces (RIS) are like a giant, smart wall of mirrors that can bend and steer radio waves to make sure your phone gets a strong signal, even if you are in a dead zone.

Traditionally, these mirrors (or "elements") were like isolated individuals: each one could only adjust its own reflection. But scientists realized that if you let these mirrors "hold hands" and talk to each other through tiny electronic circuits, they could work together much better. This is called a Beyond-Diagonal RIS (BD-RIS).

However, there's a catch. If you let everyone hold hands with everyone else, the wiring gets so tangled that you need a multi-story building (a multi-layer circuit board) just to fit the wires without them crossing. This is expensive, hard to build, and prone to breaking.

This paper asks a simple question: How can we let these mirrors hold hands as much as possible, but still keep the wiring flat enough to fit on a simple, two-layer circuit board (like a standard sandwich)?

Here is the breakdown of their solution using everyday analogies:

1. The "Flat Map" Problem (Graph Theory)

The authors used a branch of math called Graph Theory to solve this. Imagine the RIS elements are cities on a map, and the wires connecting them are roads.

The Problem: If you draw a map where every city connects to every other city, the roads will inevitably cross each other. To fix this in real life, you'd need bridges (multi-layer boards).
The Goal: They wanted to find the most connected map possible that doesn't require any bridges. In math terms, they are looking for a "Planar Graph"—a drawing where no lines cross.

2. The "Flat" Solutions

The team tested existing designs to see which ones could be drawn on a flat piece of paper without crossing lines:

The "Single-Connected" RIS: Like a group of people standing in a circle, each only holding hands with their immediate neighbor. This is very simple and flat, but not very flexible.
The "Fully-Connected" RIS: Like a party where everyone shakes hands with everyone. This is the most powerful, but the "handshakes" (wires) cross so much it requires a complex, multi-layer board.
The "Group-Connected" RIS: People are in small circles. If the circle is small (4 people or fewer), it's flat. If the circle gets too big, the wires cross.
The "Band-Connected" RIS: Imagine people sitting in a row. They can hold hands with the 3 people next to them. The authors proved that if you limit the "reach" to 3 neighbors, the wiring stays flat. If you reach for 4, it gets messy.

3. The "Maximal-Planar" Discovery

The paper's biggest contribution is finding the "Maximal-Planar-Connected RIS."
Think of this as the ultimate flat puzzle. It is the most complex, most connected design possible that still fits on a single flat layer without any wires crossing.

They found that you can connect the elements in specific patterns (like a 3-band connection or specific "central hub" patterns) that give you almost all the benefits of the super-complex "fully-connected" version, but without the manufacturing nightmare.
They call these "Maximal-Planar-Connected RISs." They are the "Goldilocks" designs: not too simple, not too messy, but just right for a standard, double-layer circuit board.

4. The Results: Performance vs. Cost

The authors ran simulations to see how well these "flat" designs work compared to the messy "fully-connected" ones and the simple "single-connected" ones.

The Fully-Connected (Messy) version: Gets the best signal, but costs a fortune to build because of the complex wiring.
The Single-Connected (Simple) version: Cheap to build, but the signal performance is poor.
The Maximal-Planar (Flat) version: This is the sweet spot. It offers a huge boost in performance compared to the simple version, getting very close to the messy, expensive version, but it can be built on a standard, cheap, two-layer circuit board.

Summary

In short, this paper is a blueprint for building smarter, cheaper wireless walls. The authors used math to figure out exactly how to wire these smart surfaces so they can talk to each other effectively without needing expensive, multi-layer circuit boards. They found the "most connected flat design" possible, ensuring that future 6G networks can be powerful without being impossible to manufacture.

1. Problem Statement

Beyond-Diagonal Reconfigurable Intelligent Surfaces (BD-RIS) represent an evolution of conventional RIS by interconnecting RIS elements via tunable impedance components. This interconnection allows for greater flexibility (e.g., full-space coverage) compared to single-connected RIS. However, existing high-performance BD-RIS architectures (such as fully-connected or large-group-connected RIS) often require a massive number of interconnections.

The Core Challenge: When the number of interconnections is large, the wiring inevitably crosses itself on a single layer. Realizing these crossings requires multi-layer Printed Circuit Board (PCB) designs with vias, which significantly increases fabrication cost, complexity, and the probability of failure.
The Goal: The authors aim to identify BD-RIS architectures that maximize performance (degrees of freedom) while being realizable on a double-layer PCB (one layer for ground, one for interconnections), thereby avoiding crossing wires and complex multi-layer fabrication.

2. Methodology

The paper employs Graph Theory to model the circuit topology of BD-RIS architectures.

Graph Modeling: The BD-RIS is modeled as a graph $G = (V, E)$ , where vertices $V$ represent RIS elements and edges $E$ represent tunable admittance interconnections between elements.
Planarity Constraint: The authors define a "Planar-Connected RIS" as an architecture whose associated graph is a planar graph. A planar graph can be drawn on a 2D plane without any edges crossing. This directly maps to the physical constraint of routing all interconnections on a single PCB layer without vias/crossings.
Analysis of Existing Architectures: The authors apply graph theory theorems (specifically Kuratowski's Theorem) to determine which existing BD-RIS topologies satisfy the planarity condition.
Optimization: They identify the class of planar-connected RISs that possess the maximum number of edges (interconnections) possible for a planar graph, known as Maximal-Planar Graphs.

3. Key Contributions

A. Characterization of Planar-Connected RIS

The paper formally defines and analyzes the planarity of various existing BD-RIS architectures:

Always Planar: Single-connected, Forest-connected, and Tree-connected RISs are always planar.
Conditionally Planar:
- Group-connected RIS: Planar only if the group size $N_G \le 4$ .
- Q-stem-connected RIS: Planar only if $Q \le 2$ .
- Q-band-connected RIS: Planar only if $Q \le 3$ .
Non-Planar: Fully-connected RIS is not planar-connected for $N \ge 5$ (as it contains a $K_5$ subgraph).

B. Proposal of Maximal-Planar-Connected RIS

The authors introduce a new class of architectures called Maximal-Planar-Connected RIS. These are planar-connected RISs that utilize the maximum possible number of interconnections allowed by planar graph theory.

Edge Limit: For $N$ elements, a planar graph can have at most $3N - 6$ edges.
Component Count: These architectures use $3N - 6$ inter-element admittances plus $N$ ground admittances, totaling $4N - 6$ tunable components.
Three Concrete Examples:
1. 3-band-connected RIS: Interconnects elements $n$ and $m$ if $|n-m| \le 3$ .
2. Central-Element + 2-band: One central element connected to all others, plus elements connected if $|n-m| \le 2$ .
3. Dual-Central + 1-band: Two central elements connected to all others, plus elements connected if $|n-m| = 1$ .

C. Performance-Complexity Trade-off Analysis

The authors evaluate these architectures in a multi-user MISO system (4 transmit antennas, 4 receivers) to compare Sum Rate vs. Circuit Complexity.

4. Results

Performance:
- Fully-connected and Band-connected (Q=7) RISs achieve the highest Sum Rate (optimal performance).
- Single-connected RIS achieves the lowest performance due to limited flexibility.
- Maximal-Planar-Connected RISs (Examples 1, 2, and 3) achieve a favorable balance. While they do not reach the absolute peak of fully-connected RISs, they significantly outperform single-connected and tree-connected RISs, approaching the performance of high-complexity band-connected RISs.
Complexity:
- Fully-connected: Complexity grows quadratically ( $O(N^2)$ ).
- Maximal-Planar-Connected: Complexity grows linearly ( $O(N)$ ), specifically $4N - 6$ components.
- Single-connected: Complexity is minimal ( $N$ components).
Key Finding: The Maximal-Planar-Connected RIS architectures offer a "sweet spot." They provide near-optimal performance gains over conventional RIS while maintaining low circuit complexity and, crucially, ensuring implementability on a double-layer PCB without crossing wires.

5. Significance

Practical Implementation: This work bridges the gap between theoretical high-performance BD-RIS designs and practical hardware constraints. It proves that high degrees of freedom can be achieved without resorting to expensive, failure-prone multi-layer PCBs.
Design Guidelines: The paper provides a rigorous mathematical framework (using graph theory) for engineers to design BD-RIS architectures that are fabrication-friendly.
Future Direction: It establishes "Maximal-Planar-Connected" as a new benchmark for low-complexity, high-performance RIS design, suggesting that future research should focus on optimizing these specific topologies for multi-user systems.

In summary, the paper demonstrates that by leveraging graph theory, one can design BD-RIS architectures that are planar (easy to fabricate on double-layer PCBs) yet maximal (offering the highest possible flexibility within that constraint), effectively solving the trade-off between circuit complexity and communication performance.