Vertical Nb Josephson junctions fabricated by direct metal deposition on both surfaces of freestanding graphene layers

Technical Summary: Vertical Nb Josephson Junctions via Freestanding Van der Waals Membranes

Problem Statement
The integration of superconducting electronics, particularly those utilizing elemental superconductors with higher transition temperatures like niobium (Nb), faces significant fabrication bottlenecks. Conventional Josephson junctions rely on amorphous oxide barriers (e.g., Al/AlOx/Al), which are incompatible with oxidation-sensitive elemental superconductors due to uncontrolled interfacial oxidation and disorder. While van der Waals (vdW) materials offer atomically flat, dangling-bond-free interfaces suitable for vertical junctions, existing fabrication methods predominantly rely on transfer-based stacking. These transfer schemes are incompatible with standard deposition-based microfabrication workflows and often fail to protect buried interfaces from ambient exposure, making the integration of oxidation-sensitive materials like Nb difficult. Furthermore, transfer-based approaches limit scalability and the ability to define junction geometry deterministically.

Methodology
The authors introduce a freestanding vdW membrane architecture that enables deposition-based fabrication of vertical Josephson junctions through double-sided processing. The core of this methodology involves:

1. Membrane Fabrication: Freestanding silicon nitride (SiNx) membranes with lithographically defined circular through-holes (1–3 µm diameter) are fabricated using standard photolithography and wet/dry etching techniques.
2. Suspended vdW Layer: Multilayer graphene (5–6 layers) is mechanically exfoliated and transferred onto the SiNx membrane, spanning the through-holes. The graphene is annealed under low vacuum to remove polymer residues, ensuring a clean interface.
3. Double-Sided Deposition:
   • Bottom Side: Nb/Au electrodes are sputter-deposited directly onto the suspended graphene. An in-situ Au capping layer prevents oxidation.
   • Top Side: After patterning the top electrode area via electron-beam lithography (EBL), Nb/Au is deposited on the top surface. The suspended graphene acts as a conformal capping layer, protecting the bottom Nb electrode from ambient exposure and oxidation during the top-side processing.
4. Junction Definition: The active junction area is defined strictly by the membrane aperture, creating a cylindrical Nb/multilayer graphene/Nb structure. Excess graphene is removed via Ar plasma etching to electrically isolate individual junctions.

Key Contributions

• Oxidation-Free Deposition: The work demonstrates a scalable route to fabricate vertical Josephson junctions using oxidation-sensitive elemental superconductors (Nb) without ambient exposure of buried interfaces. The suspended graphene layer functions simultaneously as the weak link and a protective capping layer.
• Aperture-Defined Geometry: Unlike traditional junctions defined by electrode overlap, the junction geometry is determined a priori by the lithographically defined membrane aperture. This decouples junction density and geometry from electrode patterning, allowing for independent processing of top and bottom surfaces.
• High-Quality Interface: The platform enables the formation of pristine superconductor/vdW interfaces, avoiding the disorder associated with amorphous oxide barriers.

Results

• Josephson Coupling: The fabricated devices exhibit clear Josephson coupling. Resistance measurements show a superconducting transition of the Nb electrodes at ~8 K, followed by a sharp drop to zero resistance at ~4.3 K, marking the onset of Josephson coupling.
• Transport Characteristics: At 2 K, the devices display a dissipationless supercurrent branch with a critical current ($I_c$) of approximately 110 µA and a normal-state resistance ($R_N$) of ~3.6 Ω. The product $eI_cR_N$ is ~0.4 meV, with a ratio $eI_cR_N/\Delta_0 \approx 0.46$.
• Junction Regime: The temperature dependence of the critical current, $I_c(T)$, aligns with short-junction behavior, lying between the ballistic (Kulik-Omelyanchuk KO-2) and diffusive (KO-1) limits. The Stewart-McCumber parameter ($\beta_c \approx 0.169$) indicates overdamped junction behavior, likely due to effective shunting by the normal-conducting graphene layers.
• Magnetic Interference: The devices exhibit well-defined Fraunhofer interference patterns governed by the circular aperture geometry. The data fits a circular-aperture model (Bessel function) significantly better than a rectangular model, confirming the membrane-defined cylindrical geometry.
• Sub-gap Structure: Differential conductance measurements reveal sub-gap features consistent with multiple Andreev reflections (MAR), specifically peaks at $eV \approx 2\Delta_0/n$ for $n=1$ and $n=3$. The absence of the $n=2$ peak is attributed to inelastic scattering, disorder-induced broadening, or potential asymmetry in the superconducting interfaces.
• Interface Analysis: Structural analysis of a non-functional device revealed that interfacial contamination (specifically carbon and oxygen residues from lithography) can suppress junction yield. This highlights the critical importance of interface cleanliness, particularly for the top electrode deposition.

Significance
The paper claims to establish a general, oxide-barrier-free platform for vertical superconducting heterostructures. By overcoming the limitations of transfer-based assembly and amorphous oxide barriers, this architecture enables the integration of high-$T_c$ elemental superconductors with vdW materials. The authors posit that this approach offers a scalable route to dense, uniform arrays of vertical Josephson junctions, where the junction area and density are deterministically defined by the membrane aperture rather than post-fabrication alignment. This platform is presented as extensible to other vdW materials (e.g., hBN, TMDs) and capable of supporting both proximity-coupled SNS and tunnel-type SIS junctions, thereby opening new opportunities for vertically integrated superconducting devices and circuits beyond conventional oxide-based architectures.