Closing the Loop: Resource-aware Hybrid NAS Guided by Analytical and Hardware-Calibrated Quantum Cost Modeling

1. Problem Statement

The paper addresses the critical challenge of designing Hybrid Quantum-Classical Neural Networks (HQNNs) using Neural Architecture Search (NAS). Current approaches suffer from two main limitations:

• Inadequate Cost Metrics: Traditional NAS relies on Floating-Point Operations (FLOPs) to estimate hardware costs. However, FLOPs are fundamentally unsuited for quantum layers because quantum operations are not tensor computations. FLOPs either fail to capture the true cost (e.g., in optimized simulators like lightning.qubit where FLOPs remain constant despite increasing circuit depth) or only reflect classical simulation overhead rather than actual quantum hardware execution time.
• Lack of Hardware Awareness: Most HQNN evaluations occur on ideal classical simulators, ignoring critical physical constraints of Noisy Intermediate-Scale Quantum (NISQ) devices, such as qubit connectivity limits, gate durations, noise-induced errors, and decoherence. This creates a disconnect between the designed architecture and its actual feasibility on real hardware.

2. Methodology

The authors propose a unified, time-based cost modeling framework integrated into a multi-objective NAS framework called Hyb-HANAS.

A. Unified Time-Based Cost Modeling

To bridge the gap between classical and quantum domains, the authors convert both subsystems into a common physical unit: time (seconds).

1. Analytical Classical Cost Model:

   • Instead of raw FLOPs, the model calculates classical latency by calibrating device throughput ($\Phi_{device}$) using a reference model.
   • Formula: $T_{classical} = \frac{FLOPs_{candidate}}{\Phi_{device}} \times N_{steps}$.
   • This decouples algorithmic complexity from hardware efficiency, allowing fair comparison across different devices.

2. Analytical Quantum Cost Model:

   • This is the core innovation. It estimates quantum execution time using real-time backend calibration data (from IBM Quantum devices).
   • Components:
     • Gate Execution Time: Sum of durations for 1-qubit, 2-qubit, and measurement gates based on transpiled circuits.
     • Routing Overhead: Accounts for extra SWAP gates inserted due to limited qubit connectivity (NISQ constraints).
     • Reliability Overhead: Models the statistical penalty caused by noise. Since noise corrupts results, more "shots" (repetitions) are required to obtain a valid sample. The model applies a factor of $(1 - p_{fail})^{-1}$, where $p_{fail}$ is the cumulative probability of gate errors and decoherence.
     • Gradient Evaluation: Incorporates the cost of the parameter-shift rule (requiring 2 circuit evaluations per parameter) used in real quantum training.
   • Total Cost: $C_{total} = T_{classical, total} + T_{quantum, total}$.

B. Hyb-HANAS Framework

The authors implement Hyb-HANAS, a hardware-aware NAS framework using the NSGA-II (Non-dominated Sorting Genetic Algorithm II) evolutionary search.

• Search Space: Supports two modes:
  1. Fixed CNN: Classical layers are static; only quantum architecture (qubit count, depth, entanglement topology) is optimized.
  2. Variable CNN: Both classical (CNN layers, kernels, activations) and quantum components are jointly optimized to find cross-domain co-adaptations.
• Workflow:
  1. Configuration: User defines search bounds and selects a quantum backend (Real IBM device or "Fake" simulator with calibrated noise profiles).
  2. Evaluation: Candidates are trained for a few epochs (early stopping applied).
  3. Cost Estimation: Instead of running on real hardware (which is slow/expensive), the framework uses the Analytical Quantum Cost Model to estimate the hardware cost of the candidate's transpiled circuit.
  4. Optimization: NSGA-II optimizes for three objectives: Validation Accuracy, Total Hardware Cost (Time), and Total Parameter Count.

3. Key Contributions

1. Identification of FLOPs Limitations: Demonstrated that FLOPs-based metrics fail to capture quantum computational footprints, often collapsing into uninformative Pareto fronts for hybrid models.
2. Hardware-Calibrated Analytical Cost Model: Developed a novel model that predicts quantum training latency using real backend calibration data, incorporating gate durations, routing overheads, and noise-induced sampling inefficiencies.
3. Unified Cross-Domain Metric: Created a time-based metric that allows direct comparison and joint optimization of classical and quantum components.
4. Hyb-HANAS Framework: A multi-objective NAS framework that identifies Pareto-optimal HQNN architectures, balancing accuracy with realistic hardware constraints.
5. Systematic Insights: Provided analysis on how routing overhead and noise penalties dominate costs in complex circuits and how classical-quantum co-adaptation can mitigate these penalties.

4. Results and Discussion

• Model Validation: The analytical model's time estimates closely align with IBM Qiskit's built-in scheduler (which uses calibrated pulse durations), validating its accuracy in predicting gate execution windows.
• Fixed CNN Mode: When only the quantum layer varies, the search reveals that shallow, efficient circuits can achieve accuracy comparable to deeper, more entangled circuits but with significantly lower hardware costs.
• Variable CNN Mode: Joint optimization yields a richer Pareto front. The system learns to co-adapt:
  • When the classical CNN is powerful, the search selects simpler, shallower quantum circuits to minimize routing and noise penalties.
  • When the classical CNN is lightweight, the search compensates by selecting more expressive (but costlier) quantum architectures.
• Ablation Analysis: Decomposition of costs shows that as circuit complexity increases, routing overhead (extra SWAP gates) and reliability penalties (due to noise/decoherence) become the dominant factors in total cost, often outweighing the logical gate execution time.

5. Significance

This work "closes the loop" between high-level architecture design and physical hardware constraints.

• Practicality: It enables the design of HQNNs that are actually feasible on current NISQ devices, moving beyond idealized simulations.
• Efficiency: By using an analytical model based on calibration data, it avoids the prohibitive time and cost of running thousands of NAS evaluations on real quantum hardware.
• Broader Impact: The proposed cost model is applicable beyond NAS, serving as a benchmark for quantum compilers, hardware selection, and training-time estimation for quantum algorithms.

In summary, the paper provides a rigorous, hardware-grounded methodology for designing hybrid AI systems, ensuring that the resulting architectures are not only accurate but also executable within the physical limitations of near-term quantum hardware.