A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

This paper presents the updated MIDNA ASIC, a 65 nm CMOS skipper-CCD readout chip featuring an integrated cryogenic voltage reference and improved channel isolation, which achieves sub-electron noise performance of 0.11 erms at 140 K through analog pile-up averaging.

The Gist

Imagine you are trying to listen to a single, tiny whisper in a room full of people shouting. That is essentially what scientists are doing when they hunt for Dark Matter. They use incredibly sensitive detectors called Skipper-CCDs (think of them as super-powered digital cameras) to catch the faint "whispers" of subatomic particles.

However, there's a problem: the electronics needed to read these whispers are often too big, too hot, and too noisy. If you put a giant, warm computer next to the detector, the heat and electrical interference drown out the tiny signals.

This paper introduces a new, tiny "brain" (an ASIC chip) designed to sit right next to the detector in the freezing cold, acting as a super-efficient translator that turns those whispers into clear data without adding any static.

Here is a breakdown of what this new chip does, using some everyday analogies:

1. The Problem: The "Shared Water Pipe" Issue

In the previous version of this chip, imagine four people (four data channels) trying to drink from a single water pipe. If one person takes a big gulp (a large signal), the water pressure drops for everyone else. This caused crosstalk: if a particle hit Channel 3, it would accidentally make a "ghost" signal appear on Channel 2, confusing the scientists.

The Fix: The new chip gives every single channel its own dedicated, high-pressure water pipe (a Reference Voltage Buffer). Now, if Channel 3 takes a huge gulp, Channel 2 doesn't even notice. The result? The "ghost" signals are almost completely gone, making the data much cleaner.

2. The Problem: The "Leaky Bucket"

The chip works by taking many samples of the same signal and adding them together to make the signal louder (like listening to a whisper 1,000 times to be sure you heard it). This is called Analog Pile-up.

However, the old chip had a "leaky bucket" problem. Every time it took a sample, a tiny bit of "leakage" (electrical offset) would spill into the bucket. If you took too many samples, the bucket would fill up with leakage before it even got full of the actual signal, limiting how much you could amplify.

The Fix: The engineers fixed the bucket in two ways:

• Better Seals: They added "complementary switches" (like a second set of seals) to stop the leakage.
• Bigger Bucket: They made the storage capacitor (the bucket) twice as big.
• Result: The bucket leaks so little now that you can stack up 1,200 samples without the bucket overflowing with garbage. This allows them to hear the whisper clearly even if it's incredibly faint.

3. The Problem: Bringing in a "Hot" Reference

Previously, the chip needed a stable voltage reference (a "ruler" to measure against) from a separate, external box. But putting that box inside the freezing cold chamber was difficult because standard electronics don't work well in the cold, and they can be "dirty" (radioactive), which ruins sensitive physics experiments.

The Fix: The new chip has a built-in ruler (an on-chip Bandgap Reference). It generates its own stable voltage right where it's needed. This means they don't need to bring in extra, potentially radioactive equipment, keeping the experiment pure and the setup simpler.

The Big Achievement

By combining these improvements, the team achieved something remarkable:

• Silence: They reduced the background noise so much that they can now count single electrons (the smallest possible unit of electric charge).
• Clarity: They achieved a noise level of 0.11 electrons. To put that in perspective, if the noise was a grain of sand, the signal they are looking for is a single atom.
• Scale: This tiny chip (2mm x 1mm) can handle four channels at once. This is crucial because future experiments (like the OSCURA project) plan to use 24,000 of these chips simultaneously. You can't use 24,000 giant, hot computers for that; you need tiny, cold, efficient ones like this.

In Summary

Think of this new chip as a super-smart, ultra-quiet assistant that lives right next to the detector. It filters out the noise, stops the channels from interfering with each other, and amplifies the tiniest signals so scientists can finally hear the "whispers" of Dark Matter. It's a major step forward in building the massive, sensitive detectors needed to solve one of the universe's biggest mysteries.

Technical Summary

1. Problem Statement

Skipper-CCDs are critical for sub-GeV dark matter searches (e.g., SENSEI, DAMIC-M, OSCURA) due to their ability to achieve single-electron resolution by averaging multiple non-destructive samples of the same charge. However, scaling these experiments to large arrays (e.g., 10 kg or ~24,000 sensors) presents significant challenges:

• Scalability & Power: Discrete readout electronics are too bulky and power-hungry for cryogenic environments.
• Previous ASIC Limitations: The first iteration of the MIDNA ASIC (65 nm CMOS) demonstrated low-noise capabilities but suffered from three critical design flaws:
  1. Channel Crosstalk: Channels shared a common reference voltage pad. Currents from one channel's feedback resistors caused voltage drops on the shared reference, inducing "ghost traces" in neighboring channels.
  2. Integrator Offset Accumulation: When using the "analog pile-up" technique (summing samples in the analog domain to reduce ADC speed requirements), residual offsets from the integrator accumulated with every cycle. This limited the number of samples that could be summed before saturating the output, capping the achievable noise reduction.
  3. External Dependencies: The chip relied on external voltage references and off-chip biasing resistors, which complicates cryogenic integration, introduces noise, and risks radiopurity (crucial for dark matter experiments).

2. Methodology and Design Improvements

The authors developed a second iteration of the MIDNA ASIC (MIDNA2) in a 65 nm low-power CMOS process, operating from room temperature down to 84 K. Key design modifications include:

• Per-Channel Reference Buffers:

  • Solution: A dedicated low-noise reference voltage buffer was added to each of the four channels.
  • Mechanism: This isolates the global Bandgap Reference (BGR) from individual channel currents. The buffer is a high-gain amplifier in a unity feedback configuration with a simulated output resistance of 6 mΩ.
  • Impact: Prevents voltage drops caused by one channel's activity from affecting the reference voltage of other channels.

• Optimized Integrator Stage:

  • Complementary Switches: Added in parallel with existing switches (S2–S5, Sreset) to cancel charge injection.
  • Component Scaling: Doubled the feedback capacitance (20 pF → 40 pF) and halved the resistance (75 kΩ → 37.5 kΩ) to maintain the same RC time constant while reducing the voltage impact of residual charge injection.
  • Layout Symmetry: Modified the physical layout to improve offset symmetry.
  • Impact: These changes significantly reduced the integrator's residual offset and improved symmetry when switching polarity (POL input), allowing for more samples to be summed without saturation.

• Integrated Cryogenic Bandgap Reference (BGR):

  • Solution: An on-chip low-voltage bandgap reference was designed to generate the 1.1 V reference voltage.
  • Specs: Optimized for 77 K–300 K operation, targeting <10% voltage deviation and ultra-low noise (<3 nV/√Hz white noise).
  • Impact: Eliminates the need for external cryogenic voltage regulators, reducing system complexity and improving radiopurity.

• On-Chip Integration:

  • Moved off-chip 100 kΩ biasing resistors onto the ASIC, further reducing external component count.

3. Key Results

Measurements were conducted at 140 K using a Skipper-CCD and the LTA acquisition system.

• Single-Electron Resolution:

  • The system achieved a readout noise of 0.11 $e^-_{rms}$ when averaging 1200 samples using the analog pile-up technique.
  • The noise reduction followed the theoretical $1/\sqrt{N}$ trend, confirming the capability for precise electron counting.

• Crosstalk Reduction:

  • Previous Iteration: Showed crosstalk of approximately -42 dB between channels sharing a reference pad (e.g., Channel 2 and 3).
  • Current Iteration: Crosstalk was reduced to better than -62 dB across all channel combinations. Visual inspection of particle tracks showed no "ghost" signals on neighboring channels.

• Integrator Offset Improvement:

  • The residual offset slope (accumulation per CDS cycle) was reduced by a factor of 10 (from 3.2 mV/cycle to 0.2 mV/cycle).
  • Symmetry between positive and negative integration states was significantly improved, allowing for a much larger dynamic range when summing hundreds of samples in the analog domain.

• Bandgap Reference Stability:

  • The on-chip BGR maintained a stable 1.1 V output across the 130 K–270 K range, with a variation of only ~3 mV (well within the 10% target).

4. Significance and Impact

This work represents a critical step toward the realization of massive Skipper-CCD arrays for next-generation dark matter experiments (like OSCURA).

• Scalability: By integrating four channels into a 2 mm² footprint with low power consumption (6.5 mW/channel) and eliminating external references, the ASIC enables the dense packing of thousands of sensors required for multi-kg detectors.
• Performance: The combination of sub-electron noise (0.11 $e^-_{rms}$) and high channel isolation ensures that large-scale arrays can operate without signal corruption from crosstalk or offset accumulation.
• Radiopurity: The integration of the voltage reference on-chip removes the need for external commercial off-the-shelf (COTS) components inside the cryostat, which is vital for minimizing background radiation in sensitive physics experiments.

In summary, the MIDNA2 ASIC successfully addresses the scalability and noise limitations of previous generations, providing a robust, low-noise, and highly integrated solution for the future of sub-GeV dark matter detection.