Geometry-induced correlated noise in qLDPC syndrome extraction

1. Problem Statement

Quantum Low-Density Parity-Check (qLDPC) codes, specifically Bivariate-Bicycle (BB) codes, offer high-rate quantum memory but require complex routing of qubits and gates. While existing research optimizes code parameters, syndrome extraction schedules, and decoders, it often treats the physical routed geometry (the spatial arrangement and wiring of qubits) as a fixed schematic choice rather than a variable that fundamentally alters the noise model.

The core question addressed is: Can routed geometry alone, with the code and schedule fixed, change the structure of correlated faults enough to significantly impact logical performance?

In superconducting architectures, simultaneous gate operations (same-tick) can induce crosstalk. If two gate blocks are physically close, their interaction creates correlated errors (pair faults) rather than independent single-qubit errors. The paper investigates how different geometric embeddings (e.g., monolithic single-layer vs. multi-layer biplanar) alter these correlations and whether this change can be predicted and optimized.

2. Methodology

The paper establishes a rigorous pipeline from Microscopic Physics $\to$ Retained Noise Model $\to$ Logical Performance.

A. Microscopic Interaction Model

• Hamiltonian Formulation: The authors model the geometry-induced noise as an interaction-dominated same-tick Hamiltonian:
  $$\hat{H}_{\times}(t) = J_0 \sum_{\{e,e'\} \subseteq E_t} \kappa(d_\phi(e, e')) \hat{P}_e \otimes \hat{P}_{e'}$$
  where $J_0$ is the coupling scale, $d_\phi$ is the routed distance between simultaneous gate blocks $e$ and $e'$, $\kappa$ is a proximity kernel (decaying with distance), and $\hat{P}$ are Pauli operators.
• Pauli Twirl: They apply a Pauli twirl to convert the coherent unitary evolution into a stochastic Pauli channel. This reveals that the leading-order geometry-induced effect is a correlated pair fault with probability $p(d) = \sin^2(\theta(d))$, where $\theta \propto J_0 \kappa(d)$.
• Retained Sector Model: Through Clifford propagation and ancilla elimination, they derive a "retained" channel containing only single-qubit and pair-qubit faults on data qubits. Higher-weight faults are shown to be negligible ($O(\Theta^4)$) under the specific BB schedule.

B. Geometry Metrics and Theoretical Framework

The paper introduces two distinct regimes based on the kernel type:

1. Crossing-Local Kernel ($\kappa_\times$): Only pairs with zero separation (crossings) contribute.
   • Metric: Matching Number ($\nu$). The effective fault weight on a logical support $S$ is reduced by the size of the maximum matching in the support graph: $w_{\text{eff}} = |S| - \nu$.
   • Implication: More crossings on a logical operator's support lead to a lower effective distance and higher logical error rates.
2. Strictly Positive Kernels ($\kappa > 0$): All finite separations contribute.
   • Metric: Weighted Exposure ($E_\phi^\sigma(L)$). Since the support graph becomes complete (all pairs interact), the matching number no longer distinguishes embeddings. Instead, the total weight of retained pair probabilities on the logical support becomes the discriminator.
   • Condition: For planar layouts with algebraic kernels, the coupling is summable only if the decay exponent $\alpha > 2$ (Aharonov-Kitaev-Preskill criterion).

C. Optimization Strategy

• Logical-Aware Design: The authors define an objective function $J_\kappa(\phi) = \max_{L \in \mathcal{R}_X} E_\phi^\sigma(L)$, which seeks to minimize the worst-case weighted exposure over a family of logical operators.
• Algorithm: They employ a deterministic two-swap descent (with simulated annealing warm starts) to optimize the row permutations of qubits in a single-layer layout to minimize $J_\kappa$.

3. Key Contributions

1. Derivation of Geometry-Conditioned Noise: The paper provides the first controlled derivation of a retained single-and-pair fault model specifically conditioned on routed geometry for qLDPC codes, moving beyond generic noise assumptions.
2. New Performance Metrics:
   • Effective Distance Reduction: Proves that for crossing kernels, the effective distance is $d_{\text{eff}} = d - \nu$.
   • Weighted Exposure: Identifies weighted exposure as the primary figure of merit for positive-kernel regimes where support graphs saturate.
3. Logical-Aware Optimization: Introduces a method to optimize qubit routing specifically to minimize logical error risk, rather than just minimizing wire length or latency.
4. Validation of Biplanar Architectures: Demonstrates theoretically and numerically that biplanar bounded-thickness layouts (routing different gate families in separate layers to avoid crossings) drastically suppress correlated noise compared to monolithic single-layer layouts.

4. Results

The authors validated their theory using Monte Carlo simulations on BB72 ($[[72, 12, 6]]$) and BB144 ($[[144, 12, 12]]$) benchmarks.

• Crossing Kernel Regime:

  • In a monomial (single-layer) embedding, the BB72 logical support had 15 crossings, reducing the effective distance from 6 to 3.
  • In a biplanar embedding, crossings were eliminated, preserving the effective distance.
  • Result: At coupling strength $J_0\tau = 0.04$, the monomial layout had a logical error rate (LER) of 0.253, while the biplanar layout had 0 failures (upper bound 0.00037), a >600x improvement.

• Positive Kernel Regime (Power-Law):

  • The biplanar layout reduced the worst-case weighted exposure by 44% compared to the monomial layout.
  • LER Reduction: At the reference point, the biplanar layout achieved an LER of 0.058 vs. 0.287 for monomial (a 4.9x improvement).
  • Logical-Aware Optimization: A single-layer layout optimized via the $J_\kappa$ objective reduced the worst-case exposure by 26.11% relative to the standard monomial layout, resulting in an LER of 0.205 (between monomial and biplanar).

• Correlation:

  • A strong Spearman rank correlation ($\rho_S = 0.893$) was found between Weighted Exposure and Logical Error Rate across 101 operating points, confirming that exposure is a reliable predictor of performance.
  • The hierarchy (Biplanar < Logical-Aware < Monomial) held across different coupling strengths, decay exponents, and code sizes (BB72, BB144, BB90, BB108).

5. Significance

• Paradigm Shift: The paper argues that routed geometry is a co-design variable. It is not merely a hardware implementation detail but a fundamental determinant of the noise model. Optimizing geometry alongside code and decoder is essential for qLDPC viability.
• Hardware Implications: The results strongly support multilayer/biplanar architectures for superconducting qLDPC implementations. By separating gate families into different routing layers, designers can eliminate the "crossing" mechanism that drives correlated errors, significantly boosting logical performance without changing the code or decoder.
• Decoder Compatibility: The work suggests that decoders can be improved by incorporating geometry-aware priors (correlation-aware decoders), as the standard independent-error assumption (BP+OSD) is suboptimal when geometry-induced correlations are present.
• Scalability: The findings align with the Aharonov-Kitaev-Preskill (AKP) criteria, showing that for 2D layouts, maintaining a decay exponent $\alpha > 2$ is critical for fault tolerance, and geometric optimization helps satisfy this condition by reducing effective coupling.

In conclusion, this paper provides a rigorous theoretical and empirical framework demonstrating that geometry-induced correlated noise is a dominant failure mode in qLDPC syndrome extraction, and that optimizing the physical layout (specifically using biplanar or logical-aware single-layer designs) is a necessary step to achieve practical fault tolerance.