⚡ electrical engineering

Real-Time and Scalable Zak-OTFS Receiver Processing on GPUs

This paper presents a scalable, real-time Zak-OTFS receiver architecture implemented on GPUs through hardware-algorithm co-design, which leverages delay-Doppler domain channel sparsity and optimized matrix operations to achieve high throughput and low-latency processing suitable for next-generation high-mobility communication systems.

Original authors: Junyao Zheng, Chung-Hsuan Tung, Yuncheng Yao, Nishant Mehrotra, Sandesh Mattu, Zhenzhou Qi, Danyang Zhuo, Robert Calderbank, Tingjun Chen

Published 2026-04-03

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Junyao Zheng, Chung-Hsuan Tung, Yuncheng Yao, Nishant Mehrotra, Sandesh Mattu, Zhenzhou Qi, Danyang Zhuo, Robert Calderbank, Tingjun Chen

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to send a complex message across a busy, chaotic highway where cars (signals) are zooming past at different speeds and changing lanes constantly. This is what happens in modern high-speed wireless communication, especially when you are moving fast (like in a car or on a train).

For a long time, we used a method called OFDM (think of it as sending messages in neat, separate lanes). But when things get too fast, those lanes get messy, and the message gets garbled.

Enter OTFS (Orthogonal Time Frequency Space). Instead of lanes, OTFS sends messages on a giant, flexible 2D grid (like a chessboard) that stretches across both time and speed. It's incredibly robust against the chaos of high speed. However, there's a catch: decoding this grid is like trying to solve a massive, shifting Rubik's Cube in real-time. The math is so heavy that standard computers get overwhelmed, especially when the grid gets huge to carry more data.

This paper presents a solution: A super-fast, real-time decoder built specifically for powerful graphics cards (GPUs).

Here is how they did it, explained with simple analogies:

1. The Problem: The "Rubik's Cube" of Math

The OTFS grid is huge. To decode it, you usually have to do massive matrix calculations (multiplying giant grids of numbers).

The Old Way: Imagine trying to solve a Rubik's Cube by checking every single possible move one by one. It takes forever.
The Reality: As the grid gets bigger (to send more data), the time it takes to decode grows so fast that you can't keep up with the incoming data stream. You miss the deadline, and the message is lost.

2. The Solution: Three "Cheat Codes"

The researchers used a "hardware-algorithm co-design" approach. This means they didn't just write better code; they rewrote the math to fit perfectly with how modern graphics cards (GPUs) think. They used three main tricks:

Trick A: The "Pre-Cooked Meal" (Compact Matrix Operations)

Usually, the computer has to calculate complex math formulas (like sine and cosine waves) over and over again for every single piece of data.

The Analogy: Imagine a chef who stops to calculate how much salt to add to every single grain of rice while cooking.
The Fix: The researchers realized these formulas never change for a specific setup. So, they "pre-cooked" these ingredients (calculated them once beforehand) and stored them in a compact recipe book. When the data arrives, the GPU just grabs the pre-made ingredients and mixes them instantly. This saves a massive amount of time.

Trick B: The "Sparse Map" (Exploiting Channel Sparsity)

In the real world, wireless signals don't bounce off everything. They usually bounce off a few major objects (like a building or a mountain) and ignore the rest. This means the "map" of the signal is mostly empty space (sparse).

The Analogy: Imagine trying to find a needle in a haystack. The old way was to look at every single piece of hay.
The Fix: The researchers realized the "hay" (the empty parts of the grid) doesn't matter. They built a system that only looks at the "needles" (the few active signal paths). They turned a giant, dense 10,000x10,000 grid into a tiny list of just a few important paths. This reduced the work by hundreds of times.

Trick C: The "No-Stop" Train (Branchless Iteration)

Standard computer programs often use "if-then" logic (e.g., "If the answer is good, stop; otherwise, keep going").

The Analogy: Imagine a train that stops at every station to ask the conductor, "Are we there yet?" before deciding to move to the next one. This causes traffic jams.
The Fix: GPUs hate stopping and starting. The researchers programmed the system to run a fixed number of steps (like a train running exactly 10 stops) every time, regardless of whether it "thinks" it's done early. They figured out the perfect number of stops beforehand through testing. This keeps the GPU running at full speed without any "traffic jams" caused by decision-making.

3. The Result: A Super-Express Delivery

By combining these tricks, the team built a system that:

Runs in Real-Time: It processes data fast enough to keep up with the incoming stream, even for massive grids.
Handles Huge Grids: They successfully decoded a grid size of 16,384 by 32, which is enormous compared to previous attempts.
High Speed: It achieved speeds of over 900 Mbps (megabits per second), which is fast enough to stream multiple 4K movies simultaneously.
Works on Many Devices: They tested it on everything from a powerful server chip (A100) to a small chip in a self-driving car (Jetson Orin), and it worked well on all of them.

The Big Picture

Think of this paper as the difference between trying to manually sort a million letters by hand (the old way) versus using a high-speed, automated sorting machine that only looks at the addresses that actually matter (the new way).

They took a technology (OTFS) that was theoretically amazing but practically too slow to use, and they gave it the "muscle" of modern graphics cards and the "brain" of smart math shortcuts. This paves the way for the next generation of wireless networks (6G and beyond) that can handle high-speed trains, autonomous vehicles, and massive data loads without dropping a single packet.

1. Problem Statement

Orthogonal Time Frequency Space (OTFS) modulation is a promising candidate for next-generation (NextG) high-mobility communication systems due to its robustness against high Doppler shifts compared to traditional OFDM. However, practical deployment faces two major hurdles:

Computational Complexity: OTFS operates on a 2D Delay-Doppler (DD) grid. As the grid size ( $M \times N$ ) increases to support higher bandwidths and mobility, the signal processing complexity (specifically for channel estimation and equalization) grows prohibitively, often scaling cubically or quadratically with grid dimensions.
Real-Time Latency: Existing implementations often fail to meet strict real-time processing deadlines (processing a frame within its duration) for large grid sizes. Most prior work focuses on small-to-moderate grids or functional prototypes without addressing the scalability required for high-throughput systems (e.g., grid sizes in the thousands).

The core challenge is designing a receiver architecture that can handle large DD grids (e.g., $M=16384$ ) in real-time on available hardware without sacrificing Bit Error Rate (BER) performance.

2. Methodology

The authors propose a hardware-algorithm co-design approach specifically tailored for GPU execution. The system leverages the unique properties of the Zak-OTFS domain and the parallel processing capabilities of GPUs. The methodology consists of three key pillars:

A. Compact Matrix Operations

Instead of performing standard iterative or transform-based calculations that incur high overhead, the authors precompute invariant coefficients (such as phase factors for the Zak transform) offline.

DZT/IDZT: The Discrete Zak Transform is reformulated as a single General Matrix Multiplication (GEMM) operation using a precomputed auxiliary matrix ( $E_{Zak}$ ), leveraging highly optimized GPU libraries (cuBLAS).
Channel Estimation: The estimation of the effective channel ( $\hat{h}_{eff}$ ) is reduced to a Hadamard (element-wise) product between the received signal and a precomputed twist matrix, reducing complexity to $O(MN)$.

B. Structured Sparsity (SS) Exploitation

The paper identifies that the wireless channel in the DD domain is inherently sparse (limited number of propagation paths) and possesses a structured pattern.

Structured Sparsity: Rather than constructing the full dense channel matrix $\mathbf{H}_{dd}$ (size $MN \times MN$ ), which is memory-prohibitive, the system represents the channel using only the dominant paths.
Efficient MVM: The channel matrix is decomposed into a set of path-induced circular shifts. Matrix-Vector Multiplications (MVM) required for equalization are approximated by summing only the $P$ dominant paths (where $P \ll MN$ ). This reduces the complexity of MVM from $O((MN)^2)$ to $O(PMN)$.
Memory Reduction: This approach reduces memory requirements from storing dense matrices (e.g., hundreds of GBs for large grids) to storing only path indices and coefficients ($O(PMN)$).

C. Compute-Aware Iterative Equalizer (CGA)

The authors implement a Conjugate Gradient Algorithm (CGA) equalizer optimized for GPU architecture:

Branchless Execution: Traditional CGA uses dynamic early termination based on residual norms, which causes costly CPU-GPU synchronization and branch divergence on GPUs. The authors replace this with a fixed-iteration strategy determined by offline profiling.
BER-Driven Profiling: The optimal number of iterations is pre-calculated based on Signal-to-Noise Ratio (SNR) and grid size to ensure the desired BER is met without unnecessary computation.
Domain Selection: The equalization is performed directly in the DD domain to avoid the overhead of transforming between DD and frequency domains.

3. Key Contributions

First Real-Time Large-Scale Implementation: The paper presents the first implementation achieving real-time Zak-OTFS processing for DD grid sizes up to $(16384, 32)$ , a scale previously considered infeasible for real-time DSP.
Hardware-Aware Algorithm Design: It introduces a novel "Structured Sparsity" representation that aligns the mathematical structure of the OTFS channel with GPU memory access patterns, drastically reducing both arithmetic complexity and memory footprint.
Branchless Equalization: It proposes a branchless, fixed-iteration CGA equalizer that eliminates synchronization bottlenecks, ensuring predictable latency and high GPU utilization.
Comprehensive Evaluation: The system is evaluated across a wide range of hardware (Intel Xeon CPU, NVIDIA Jetson Orin, RTX 6000 Ada, A100, H200) and channel conditions (Vehicular-A model), demonstrating robust scalability.

4. Results

The proposed system was evaluated under a 245.76 MHz bandwidth with 16QAM modulation:

Throughput: Achieved a peak throughput of 906.52 Mbps with a DD grid of $(16384, 32)$ . With QPSK, it achieved 491.44 Mbps.
Latency: The system consistently met the 99.9th percentile real-time processing deadline of 2.13 ms (corresponding to a frame duration of ~1.07 ms) even at the largest grid sizes.
Scalability:
- On high-end GPUs (A100, H200), the system maintained low latency as grid size increased, whereas CPU-based implementations failed to scale beyond small grids.
- The structured sparsity approach reduced the memory requirement for the channel matrix by over 300x compared to dense representations for a $(48, 32)$ grid, and would be even more significant for larger grids.
Performance: The SS-CGA equalizer achieved BER performance comparable to the optimal (but computationally expensive) LMMSE equalizer and significantly better than the MRC equalizer, without the high latency of LMMSE.

5. Significance

This work bridges the gap between theoretical OTFS benefits and practical hardware implementation. By demonstrating that OTFS can be processed in real-time on GPUs with massive grid sizes, it validates OTFS as a viable waveform for NextG high-mobility scenarios (e.g., high-speed trains, UAVs, and vehicular communications). The techniques developed—specifically the structured sparsity exploitation and branchless GPU kernel design—offer a blueprint for implementing other complex, large-scale signal processing algorithms in future wireless systems. The open-sourcing of the code and benchmarks further accelerates research in this domain.