L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference

1. Problem Statement

Spiking Neural Networks (SNNs) are promising for energy-efficient edge intelligence due to their sparse, event-driven nature. However, deploying SNNs on hardware faces three critical bottlenecks:

• Memory Overhead: The temporal nature of spike-based computation requires repeated storage and updates of membrane potentials across timesteps, leading to significant data movement and memory usage.
• Inefficient Scaling: Existing quantization techniques often focus solely on weight precision while neglecting system-level inefficiencies caused by scaling operations and temporal dataflow.
• Limited Parallelism & Precision Adaptability: Prior hardware accelerators often lack a unified architecture that supports multi-precision execution (e.g., 2-bit, 4-bit, 8-bit) and efficient SIMD (Single Instruction, Multiple Data) parallelism within a single datapath. Many designs rely on multipliers or complex approximations (like CORDIC) that increase area and power consumption.

2. Methodology: L-SPINE Architecture

The authors propose L-SPINE, a low-precision, SIMD-enabled spiking neural compute engine designed for resource-constrained edge devices. The architecture is implemented on an AMD VC707 FPGA.

A. System-Level Architecture

• Integrated Controller: A tightly coupled pico-rv32 RISC-V CPU orchestrates data movement, scheduling, and synchronization.
• 2D Processing Array: The core consists of a scalable 2D array of Neuron Compute Engines (NCEs).
• Dataflow Optimization: The system utilizes a ring-based FIFO interface to minimize access latency. It exploits temporal reuse of membrane potentials and spatial reuse of synaptic weights to reduce bandwidth requirements.
• Modules: Includes spike encoders, spike buffers, leak Finite State Machines (FSM), and spike counters to manage event-driven execution.

B. SIMD Multi-Precision Compute Engine (NCE)

The core innovation is a unified, reconfigurable datapath that supports 2-bit, 4-bit, and 8-bit operations dynamically.

• Multiplier-Less Design: Instead of using hardware multipliers, the architecture employs a shift-add model.
  • Synaptic Accumulation: Input spikes (binary events) are accumulated with quantized weights using a hierarchy of 1-bit full adders arranged in a bit-serial/parallel hybrid configuration.
  • Neuron Dynamics: Membrane potential updates (leakage behavior) are modeled using shift-based operations, eliminating multipliers entirely.
• Configurable Precision: A Precision Control (PC) signal dynamically reconfigures the datapath to perform:
  • 16 parallel 2-bit operations (INT2).
  • 4 parallel 4-bit operations (INT4).
  • 1 parallel 8-bit operation (INT8).
• Components: Includes an Accumulation (AC) unit, a Leaky Integrate-and-Fire (LIF) unit, local scratchpad memories (Spads) for weights and states, and a comparator for thresholding.

C. Design Flow

• Training: SNN models are trained using standard backpropagation (BPTT) and surrogate gradient learning.
• Quantization: Post-training quantization is applied to convert weights and parameters to INT2, INT4, or INT8.
• Implementation: The design is synthesized using parameterized RTL and mapped to the FPGA.

3. Key Contributions

1. Unified Multi-Precision SIMD Engine: A single datapath capable of parallel execution for 2/4/8-bit SNN operations, offering up to 16× parallelism for INT2, significantly boosting throughput for low-bit inference.
2. Compact Multiplier-Less Neuron: A highly efficient neuron implementation requiring only 459 LUTs and 408 Flip-Flops, with a critical delay of 0.39 ns and 4.2 mW power per neuron.
3. Scalable System Integration: A complete accelerator integrating a RISC-V controller and 2D array, achieving 2.38 ms latency with 0.54 W total power.
4. Quantization Analysis: Demonstrated that aggressive low-bit quantization (INT2/INT4) drastically reduces memory footprint with minimal accuracy loss compared to FP32 baselines.

4. Results and Performance Evaluation

Hardware Efficiency (FPGA Implementation)

• Resource Utilization: The proposed neuron uses significantly fewer resources than state-of-the-art (SOTA) designs (e.g., 459 LUTs vs. 1,770 LUTs in TVLSI'26).
• Speed & Power: Achieves a critical path delay of 0.39 ns and consumes 4.2 mW per neuron, outperforming designs like TCAS-II'24 (4.62 ns, 22.5 mW).
• System Level: The full accelerator consumes 0.54 W with a latency of 2.38 ms.

Comparison with CPU/GPU

L-SPINE demonstrates orders-of-magnitude improvements in latency and energy efficiency compared to general-purpose platforms:

• VGG-16 Inference:
  • CPU (Intel i7): 23.97 seconds (125 W).
  • GPU (GTX 1050Ti): 10.15 seconds (75 W).
  • L-SPINE (INT2): 4.83 milliseconds (0.54 W).
  • L-SPINE (INT8): 16.94 milliseconds (0.54 W).
• ResNet-18 Inference:
  • CPU: 34.43 seconds.
  • GPU: 10.26 seconds.
  • L-SPINE (INT2): 7.84 milliseconds.

Accuracy vs. Memory Trade-off

• INT8: Closely matches FP32 baseline performance.
• INT4/INT2: Exhibit graceful accuracy degradation while reducing memory footprint significantly. For example, INT2 configurations reduce memory requirements by a large margin while maintaining competitive Top-1 accuracy on datasets like CIFAR-10 and ImageNet.

5. Significance

The L-SPINE architecture addresses the critical gap between the theoretical efficiency of SNNs and their practical hardware deployment. By combining SIMD parallelism with a multiplier-less, shift-add datapath, it achieves:

• Real-Time Edge AI: Reduces inference latency from seconds (CPU/GPU) to milliseconds, enabling real-time applications.
• Extreme Energy Efficiency: Achieves up to three orders of magnitude improvement in energy efficiency compared to CPU/GPU baselines, making it ideal for battery-powered edge devices.
• Scalability: The unified, reconfigurable design allows the same hardware to adapt to different precision requirements (INT2 to INT8) without redesigning the silicon, offering a flexible solution for next-generation neuromorphic systems.

In conclusion, L-SPINE establishes a new benchmark for resource-efficient SNN accelerators, proving that low-precision, event-driven computing can be implemented with high throughput and minimal hardware cost on standard FPGA platforms.