SiGe/Si(111)/SiGe heterostructure for Si spin qubits with electrons confined in L valley of conduction band

1. Problem Statement

Silicon-based electron spin qubits are a leading candidate for quantum computing due to compatibility with CMOS technology. However, conventional devices using Si(001) crystals face a critical stability issue:

• Valley Degeneracy: In Si(001), the conduction band minimum is at the $\Delta$ valley, which is sixfold degenerate. Under biaxial tensile strain, this splits into a fourfold excited state and a doubly degenerate ground state.
• Pseudo-degeneracy: The energy splitting between these two ground states (valley splitting) is unstable and highly sensitive to atomic-level thickness variations, typically ranging from 20 $\mu$eV to 300 $\mu$eV.
• Qubit Interference: This instability creates a "pseudo-degeneracy" that competes with the Zeeman splitting (spin splitting) required for qubit operation. If the valley splitting is comparable to or smaller than the Zeeman energy, it disrupts the two-level system essential for a qubit.

Current attempts to increase valley splitting in Si(001) have not yet provided a robust solution. The authors propose shifting the conduction band minimum to the L valley in Si(111) crystals, which offers a non-degenerate ground state, thereby eliminating the pseudo-degeneracy problem.

2. Methodology

The authors employed a theoretical approach combining deformation potential theory and quantum confinement effects to analyze the Si$_{1-x}$Ge$_x$/Si(111)/Si$_{1-x}$Ge$_x$ heterostructure.

• Strain Analysis (Deformation Potential Theory):

  • Calculated the energy shifts of the $\Delta$ and L valleys under biaxial tensile strain ($\varepsilon_{\parallel}$) applied to the Si(111) plane.
  • Included both first-order linear terms (using standard deformation potentials $\Xi_d$ and $\Xi_u$) and second-order nonlinear terms (accounting for internal strain parameters and high-strain nonlinearity).
  • Used the elastic stiffness tensor to relate in-plane strain to out-of-plane strain ($\varepsilon_{\perp}$).

• Quantum Confinement Modeling:

  • Modeled the Si layer as a finite potential well with barrier height $V_0 = 0.28$ eV (based on Ge/Si(111)/Ge offset).
  • Solved the Schrödinger equation for electrons confined in the well to determine quantized energy levels ($E_q$) for the L1, L3, and $\Delta_6$ valleys.
  • Used effective masses ($m^*$) specific to the Si(111) orientation for both the well (Si) and barrier (SiGe) regions.

• Feasibility Analysis:

  • Calculated the critical thickness ($h_c$) for plastic relaxation using the People-Bean (P-B) model (energy equilibrium model), which is more accurate for high lattice mismatches than the Matthews-Blakeslee model.
  • Determined the required Germanium (Ge) concentration ($x$) in the Si$_{1-x}$Ge$_x$ barrier to achieve the necessary strain.

• Sensitivity Analysis:

  • Tested the robustness of the results by introducing $\pm 10\%$ variations in deformation potential coefficients and nonlinear terms.

3. Key Contributions

• Proposal of a New Qubit Architecture: Introduction of a SiGe/Si(111)/SiGe heterostructure where the electron is confined in the L valley of the Si(111) conduction band.
• Elimination of Pseudo-degeneracy: Demonstration that the L valley ground state (L1) in Si(111) under biaxial tensile strain is non-degenerate (singlet), while the excited state (L3) is triply degenerate. This removes the unstable pseudo-degeneracy found in Si(001).
• Critical Strain and Thickness Thresholds: Precise calculation of the conditions required to shift the conduction band minimum from the $\Delta$ valley to the L valley.
• High Mobility Potential: Identification that the effective mass of electrons in the L1 valley within the (111) plane is extremely light ($0.12m_0$), suggesting potential for ultra-high-speed Field Effect Transistors (FETs) in addition to qubits.

4. Key Results

• Energy Reversal Condition:

  • The energy of the L1 valley decreases rapidly with tensile strain, while the $\Delta_6$ valley energy increases.
  • For a Si(111) layer thickness of $t \le 4$ nm, the energy crossover ($E_{L1} < E_{\Delta6}$) occurs when the biaxial tensile strain exceeds approximately 3.9%.
  • At this crossover, the L1 ground state is roughly 72 meV lower than the $\Delta_6$ valley, a gap significantly larger than the Zeeman splitting ($\sim$ tens of $\mu$eV), ensuring a stable two-level system.

• Material Requirements:

  • To achieve >3.9% strain, the Ge concentration ($x$) in the Si$_{1-x}$Ge$_x$ barrier must be $x \ge 0.94$ (nearly pure Ge).
  • For a 3 nm Si layer, the critical Ge concentration is $x \approx 0.935$.

• Structural Feasibility:

  • The calculated critical thickness ($h_c$) for plastic relaxation (dislocation formation) for Si(111) on highly Ge-rich SiGe is greater than 3 nm.
  • This confirms that a structure with $x \ge 0.94$ and $t \le 4$ nm is theoretically feasible without strain relaxation.

• Robustness:

  • Sensitivity analysis showed that even with $\pm 10\%$ variations in deformation potentials and nonlinear coefficients, the L1 valley remains the ground state for $t \le 4$ nm in a Ge/Si(111)/Ge structure.

5. Significance and Implications

• Stable Qubits: This architecture solves the "valley splitting instability" problem inherent in Si(001) qubits by utilizing a naturally non-degenerate ground state, potentially leading to more reliable and scalable silicon spin qubits.
• High-Speed Electronics: The extremely low effective mass ($0.12m_0$) in the L1 valley suggests that this material system could also enable next-generation high-speed electronic devices, not just quantum devices.
• Fabrication Challenges & Solutions:
  • The paper acknowledges the difficulty of growing flat Si layers on nearly pure Ge due to the Stranski-Krastanov (island) growth mode.
  • Proposed Solution: Utilize low-temperature epitaxial growth (300°C–400°C) via MBE or CVD to suppress island formation and prevent Ge diffusion into the Si layer.
  • Integration Strategy: Since high-temperature processing is incompatible with this structure, the authors suggest fabricating the qubit layer separately or before CMOS integration, followed by low-thermal-load annealing (e.g., RTA).

In conclusion, the paper provides a rigorous theoretical foundation for a new class of silicon-based quantum devices that leverage the unique band structure of strained Si(111) to overcome fundamental limitations of current Si(001) qubit designs.