Reconfigurable and cascaded logic gates using dual-input multilayered heater nanocryotrons

Technical Summary: Reconfigurable and Cascaded Logic Gates Using Dual-Input Multilayered Heater Nanocryotrons

Problem Statement
Superconducting electronics offers a promising platform for ultra-low-power, high-speed digital circuits, particularly for applications requiring cryogenic integration, such as quantum computing and single-photon detection. While existing superconducting devices like Nanocryotrons (nTrons) and Single Flux Quantum (SFQ) circuits provide high performance, they face significant challenges regarding scalability, fan-out, and interface difficulties. Specifically, nTrons rely on direct electrical coupling between control and channel elements, which limits bias margins and isolation. In contrast, heater-electric thermal switches (hTrons) offer complete electrical isolation but have historically been restricted to fixed logic functions. Most current cryogenic logic architectures are limited to specific Boolean operations or require analog current summation within shared thermal regions, lacking the structural independence and dynamic reconfigurability necessary for scalable, flexible computing systems.

Methodology
The authors present a dual-input, multilayered Heater Nanocryotron (hTron) designed to integrate multi-input functionality and logic reconfigurability within a single device. The device architecture consists of a superconducting Niobium-Titanium-Nitride (NbTiN) nanowire channel (400 nm wide), separated by a thin (~40 nm) insulating layer of PECVD-SiO2 from two independent metal heaters (70 nm wide). This multilayer design ensures electrical isolation between the heaters and the channel, with heat transfer occurring via phonons.

The operating principle relies on Joule heating generated by the two independent heaters. When the local temperature of the nanowire exceeds its critical threshold (determined by the channel bias current), a resistive hotspot forms, interrupting superconductivity and generating a measurable output voltage. The logic state is determined by the interplay between the channel bias current and the combined thermal energy of the heaters.

To characterize the device, the authors employed both DC and AC measurement setups. They systematically varied the bias current applied to the superconducting channel while independently controlling the currents through the two heaters. This enabled them to map the device response across various bias ranges to observe transitions between logic behaviors. To demonstrate scalability, the authors cascaded two hTron units. This was first performed using off-chip instrumentation (amplifiers and attenuators) to condition signals between room temperature and cryogenic environments, and subsequently demonstrated in a fully integrated on-chip configuration where the output of one hTron directly drove the input of another without external signal conditioning.

Main Contributions and Results

1. Reconfigurable Logic Capability: The primary contribution is the demonstration that a single dual-heater hTron can dynamically switch between different logic functions without physical modification.
   • AND/OR Reconfigurability: By adjusting the channel bias current, the device can be configured as an AND gate (requiring both heaters to be active to switch to the resistive state) or as an OR gate (where a single heater suffices to trigger switching).
   • Universal Logic Gates: By changing the circuit configuration (specifically readout termination and biasing), it was demonstrated that the device also functions as NAND and NOR gates. The authors note that NAND and NOR are universal logic gates, implying that the device can construct any Boolean circuit.
2. Cascading and Scalability: The study successfully demonstrated that the output of one hTron can drive another.
   • Off-Chip Cascading: A dual-input hTron was driven by the output of a preceding hTron, successfully realizing a three-input AND function ($A \cdot B \cdot C$).
   • On-Chip Integration: A fully integrated configuration was achieved where the output of the first stage directly triggered the second stage within the cryostat. This confirmed the potential to stack these devices to perform complex decision-making processes.
3. Experimental Verification: The authors provided experimental data showing clear transitions between superconducting (logic high/low, depending on configuration) and resistive states. Time-domain measurements confirmed the expected logic operations (AND, OR, NAND, NOR) and successful signal transmission through cascaded stages.

Significance and Claims
The work claims that this dual-input hTron represents a step forward in realizing complex, scalable superconducting computing architectures. The significance of the work lies in its ability to:

• Reduce Circuit Complexity: By enabling a single hardware platform to perform various logic operations (AND, OR, NAND, NOR) through dynamic biasing instead of fixed layouts, the design reduces redundant circuit area and simplifies interconnection networks.
• Improve Integration: The complete electrical isolation between heaters and channels eliminates leakage current problems found in other architectures, while the demonstrated cascading capability suggests these devices can serve as building blocks for larger, programmable logic systems.
• Enable Cryogenic Processing: The ability to perform logic operations and signal routing entirely within the cryogenic environment is highlighted as a critical advantage for interfacing with superconducting sensors (such as SNSPDs) and quantum computing systems, potentially eliminating the need for multiple conversion stages between cryogenic and room-temperature environments.

The authors conclude that, although the current work focuses on basic logic gates and simple cascading, the inherent reconfigurability and scalability of the hTron make it a suitable candidate for future energy-efficient, low-noise computing architectures, including those inspired by neural networks.