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A 0.08 pJ/bit 56 GBaud Monolithic Optical Receiver Front End for IMDD Photonic Links

This paper presents the design, fabrication, and validation of a monolithic silicon photonic optical receiver front end in the GlobalFoundries FotonixTM platform that achieves 28.9 GHz bandwidth and 0.08 pJ/bit energy efficiency while supporting 56 GBaud IMDD transceivers with low noise and power consumption.

Original authors: Robert P. Pesch, Arjun Khurana, Joshua J. Wong, Joel Slaby, Stephen E. Ralph

Published 2026-05-11

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Robert P. Pesch, Arjun Khurana, Joshua J. Wong, Joel Slaby, Stephen E. Ralph

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to listen to a whisper in a very loud, crowded room. The person whispering is a tiny light sensor (a photodiode) on a computer chip, and the "crowd" is all the electrical noise that naturally happens in electronics. Your goal is to hear that whisper clearly, turn it into a loud shout that a computer can understand, and do it all while using as little battery power as possible.

This paper describes the team's success in building a super-efficient "hearing aid" for light-based data connections. Here is how they did it, broken down into simple concepts:

1. The Challenge: The "Heavy Backpack" Problem

In the world of high-speed internet and AI data centers, data is moving incredibly fast (56 billion times a second, or 56 Gbaud). To move this data, we use light. However, the electronic circuits that catch this light and turn it back into numbers usually act like a heavy backpack: they are bulky, they get hot, and they drain a lot of power.

The authors wanted to build a receiver that is so light and efficient it could be used in places where power is scarce, like satellites in space or massive AI data centers that are already running hot.

2. The Solution: A "Monolithic" Team

Instead of building the receiver out of separate parts glued together (which creates messy connections and slows things down), they built the entire team on a single piece of silicon. Think of it like building a house where the kitchen, bedroom, and bathroom are all carved out of one giant block of stone, rather than building three separate shacks and connecting them with a long, wobbly bridge.

This "monolithic" approach means the light sensor and the amplifier are right next to each other, reducing the distance the signal has to travel and cutting out the "static" that usually happens at the connection points.

3. The "Hearing Aid" Design (The Circuit)

The team designed a three-part system to handle the signal:

The Ear (Photodiode): This catches the light. In their design, it's made of Germanium, which is very good at catching light signals.
The Amplifier (The TIA): This is the most important part. It takes the tiny electrical current from the light and boosts it. The team used a special design called "Active Voltage-Current Feedback." Imagine a smart microphone that doesn't just turn up the volume; it actively cancels out the background noise while boosting the voice. They tuned this part to be very fast but also very quiet.
The Shouter (Post-Amplifier & Buffer): Once the signal is boosted, it needs to be strong enough to travel to the next computer chip. This stage acts like a megaphone, making the signal loud and clear without distorting it.

4. The Secret Sauce: "Micro-Layout"

The paper emphasizes that how they drew the tiny transistors on the chip mattered just as much as the math.

The Problem: If you draw a wide transistor like a single long road, electricity has to travel a long way to get through, creating resistance (traffic jams).
The Fix: They used a "multi-finger" layout. Imagine instead of one long road, they built a parking lot with many short, parallel lanes. This lets the electricity flow much faster and with less resistance. They combined this with a "parallel" strategy, stacking these lanes to create a super-highway for the signal. This allowed them to keep the circuit fast without making it huge.

5. The Results: Super Efficient

When they tested their creation, the results were impressive:

Speed: It can handle data speeds up to 64 Gbaud (which is incredibly fast, like downloading a movie in a split second).
Power: It uses almost no energy. They measured it at 0.08 picojoules per bit. To put that in perspective, it's like the energy required to lift a single grain of sand a microscopic distance.
Noise: It is very quiet. It can hear the "whisper" of the light signal without adding its own static.
Size: The entire chip is tiny, fitting easily on a fingernail.

Why This Matters

The paper claims this device is a breakthrough for two specific areas:

AI Data Centers: These places need to move massive amounts of data between computers. If every connection uses less power, the whole building runs cooler and cheaper.
Aerospace (Satellites): Satellites have very strict limits on how much power they can carry and how much heat they can get rid of (since there is no air to cool them down). This tiny, cool-running receiver is perfect for them.

In short, the authors built a tiny, ultra-fast, ultra-efficient light-to-electricity converter that uses a clever layout to minimize waste, making it ideal for the next generation of super-fast, power-hungry technology.

Technical Summary: A 0.08 pJ/bit 56 GBaud Monolithic Optical Receiver Front End for IMDD Photonic Links

Problem Statement
High-capacity optical links are increasingly critical for Artificial Intelligence (AI) datacenters and aerospace platforms. However, scaling these systems is constrained not only by bandwidth but also by power consumption, thermal management, and integration complexity. In datacenters, receiver power contributes significantly to heat density and cooling demands. In aerospace, stringent Size, Weight, Power, and Cost (SWaP-C) limits and the lack of convective cooling make active thermal control solutions (like TECs) undesirable due to their power overhead. While Intensity Modulated Direct Detect (IMDD) links offer low latency and power efficiency, deployed optical transceivers still face challenges regarding power dissipation, heat, and packaging complexity. The authors address the need for a monolithic optical receiver analog front end (AFE) that achieves low power consumption, low noise, and wide bandwidth to support 56 GBaud transceivers without the parasitic penalties of hybrid packaging.

Methodology
The design approach prioritizes a monolithic, layout-driven strategy within the GlobalFoundries Fotonix™ silicon photonics platform to minimize parasitics and system complexity.

Circuit Topology Selection:
- Photodiode (PD): Utilizes a germanium photodiode native to the platform (~0.9 A/W responsivity, 40 GHz bandwidth).
- Transimpedance Amplifier (TIA): The authors selected a modified Active Voltage-Current Feedback (AVCF) topology. This choice balances bandwidth and Input Referred Noise Current (IRNC) while minimizing power. The design avoids inductors to save footprint. Small-signal analysis modeled the TIA as a second-order low-pass filter, allowing for controlled gain peaking to extend bandwidth without compromising stability.
- Post-Amplifier (PA) and Output Buffer (OB): A cascaded chain of Cherry-Hooper amplifiers (CMOS inverters with resistive feedback) provides additional voltage gain and impedance matching. The stages follow an exponential horn structure to increase current sourcing capability toward the output.
- Noise Optimization: The design focuses on minimizing IRNC. By ensuring high TIA gain, the noise contributions from subsequent PA and OB stages are rendered negligible when referred to the input.
Physical Design and Layout Optimization:
- The authors employed a $g_m/I_D$ methodology for initial transistor sizing.
- To mitigate layout parasitics (stray capacitance and routing resistance) that degrade high-frequency performance, a specific unit-cell layout configuration was developed. Instead of simple or standard multi-finger layouts, the design utilizes a multiple parallel multi-finger device structure. This combines the compact footprint of multi-finger devices with the reduced effective gate resistance of parallel transistors.
- Full-wave 3D simulation tools were used to extract parasitics and refine the design iteratively, ensuring the post-layout performance met targets.

Key Contributions

Architecture: A monolithic integration of a germanium photodiode, a modified AVCF TIA, and cascaded Cherry-Hooper amplifiers.
Layout Technique: A systematic transistor unit-cell layout (4 parallel transistors, each with 8 fingers) specifically optimized to reduce gate resistance and parasitic capacitance in a high-speed CMOS process.
Performance Targets: The design targets a total transimpedance gain of ~60 dBΩ, a bandwidth sufficient for 56 GBaud operation, and ultra-low power consumption (<10 mW).

Experimental Results
The fabricated device was characterized via DC operation, noise measurement, and time-domain eye diagrams.

Power Consumption: Operating at a 1.2 V supply, the circuit consumes 9.22 mW (7.68 mA). At a lower 0.9 V supply, it consumes 2.5 mW while supporting 32 GBaud.
Bandwidth and Gain: Post-layout simulations predicted 28.9 GHz bandwidth and 61.7 dBΩ gain. The measured electrical characterization confirms the design supports high-speed operation.
Noise: The measured RMS integrated input-referred noise current is less than 737 nA, corresponding to a sensitivity of -19.57 dBm for a BER of $10^{-12}$ (assuming ideal conditions).
Data Rate Validation: Electrical eye diagrams were measured up to 64 GBaud.
- OOK-NRZ: Error-free performance (accounting for Forward Error Correction) was demonstrated at 32 and 56 GBaud.
- PAM-4: Clear signal levels were discernable at 64 GBaud, though error-free operation required additional equalization.
Energy Efficiency: The system achieves an energy efficiency of 0.08 pJ/bit at 56 GBaud PAM-4.

Significance and Claims
The paper claims that this design achieves the lowest energy per bit (0.08 pJ/bit) among the reviewed state-of-the-art optical receivers. While the transimpedance gain (61.7 dBΩ) is modest compared to some high-gain designs, the low noise floor enables high sensitivity (-19.57 dBm), comparable to the best reviewed literature. The authors emphasize that the monolithic CMOS approach, despite having a lower transit frequency ( $f_t$ ) than SiGe BiCMOS, offers superior system-level performance by eliminating wire-bond inductance and discrete photodiode capacitance issues. The compact die area (650 µm x 750 µm total, with a 20 µm x 135 µm core) supports ultra-dense integration, making the design particularly suitable for power-constrained AI datacenters and aerospace platforms. The work validates the utility of monolithic electronic-photonic transceivers for future SWaP-C constrained applications.