💻 computer science

Energy-Efficient Implementation of Spiking Recurrent Cells on FPGA

This paper presents an FPGA accelerator for Spiking Recurrent Cell (SRC) neurons that achieves a balance between biological plausibility and hardware efficiency by employing mathematical simplifications to eliminate costly operations, demonstrating competitive accuracy (up to 96.31%) and significant energy savings (down to 0.45 mJ per digit) on the MNIST dataset.

Original authors: Pascal Harmeling, Florent De Geeter, Guillaume Drion

Published 2026-05-13

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Pascal Harmeling, Florent De Geeter, Guillaume Drion

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to teach a computer to recognize handwritten numbers, like the digits on a bank check. Usually, computers do this using "Artificial Neural Networks" (ANNs), which are like massive, always-on factories. They run 24/7, checking every single piece of data constantly, even when there's nothing important to see. This is powerful, but it eats up a lot of electricity, like leaving all the lights in a stadium on just to watch one person walk across the field.

The "Spiking" Alternative
Nature has a better way. Our brains don't run on constant electricity; they work on "spikes." Think of a neuron like a firecracker. It sits quietly until it gets enough "noise" (input), and then it pops (fires a spike). Between pops, it's silent. This "event-driven" approach is incredibly energy-efficient because the brain only uses power when something actually happens.

Scientists have been trying to build computer chips that work like this "Spiking Neural Network" (SNN). However, there's a catch:

Too Simple: Some models are like a basic light switch (on/off). They are easy to build on computer chips but miss the subtle nuances of how real brains work.
Too Complex: Other models try to copy the brain perfectly, but they are so complicated that building them on a chip is like trying to build a Ferrari engine out of LEGOs—it takes too much space and power.

The Paper's Solution: The "SRC" Neuron
This paper introduces a middle-ground solution called the Spiking Recurrent Cell (SRC). Think of the SRC as a "smart firecracker." It's not just a simple switch, but it's not a full-blown Ferrari engine either. It captures the complex, rhythmic behavior of a real brain cell but is designed to be built efficiently on a specific type of computer chip called an FPGA (Field-Programmable Gate Array). You can think of an FPGA as a "Lego board for electronics" that you can reprogram to do different jobs instantly.

How They Made It Efficient
Building this "smart firecracker" on a chip is tricky because chips hate complex math. The original math for these neurons involves fancy functions (like tanh and exp) that are like trying to calculate the exact curve of a rainbow using a calculator that only does addition.

The authors came up with a clever set of shortcuts:

Ditching the Fancy Math: Instead of calculating complex curves, they replaced them with simple, straight-line approximations. It's like drawing a smooth curve by connecting a few straight dots; it looks almost the same but is much faster to draw.
No Decimals: Computers hate floating-point numbers (decimals) because they take up a lot of space. The team scaled everything up by 1,000 and used whole numbers (integers) instead. It's like measuring a room in millimeters instead of meters to avoid decimals, then just remembering to divide by 1,000 at the end.
The "Switch" Trick: One part of the math was a complex formula that decided whether the neuron was "fast" or "slow." The authors realized this formula was just a fancy way of saying, "If the input is above X, be fast; otherwise, be slow." They replaced the complex formula with a simple "If/Then" switch, which is very cheap for a chip to build.

The Experiment
They built this system on a chip called an Artix-7 and tested it using the MNIST dataset (a standard collection of 70,000 handwritten digits).

The Setup: They didn't feed the chip a static image. Instead, they turned the image into a "Spiking Trace"—a short movie of 220 frames where pixels flicker on and off like Morse code.
The Result: The chip recognized the digits with 96.31% accuracy. This is excellent and comparable to much more complex systems.

The Energy Trade-Off
The real magic happened when they started tweaking the system to save even more energy:

Shorter Movies: They realized they didn't need the full 220-frame movie to recognize a number. They shortened it to just 44 frames. The chip got faster and used less energy, though accuracy dropped slightly (to about 92.9%).
Smaller Weights: In a neural network, "weights" are the strength of the connections between neurons. Usually, these are stored with high precision (like 9 bits). The authors showed they could shrink these down to just 4 bits (like changing from a high-definition photo to a pixelated sketch). This saved a lot of memory and power.
The Sweet Spot: By combining a shorter movie (44 frames) and smaller weights (4 bits), they achieved 92.89% accuracy while using only 0.45 millijoules of energy per digit. To put that in perspective, that's a tiny fraction of the energy used by standard computer methods.

Why This Matters
The paper demonstrates that you don't have to choose between "biologically accurate" and "energy efficient." By using the SRC model and these clever math shortcuts, they built a system that:

Thinks like a brain (using spikes and continuous dynamics).
Runs like a machine (using simple, fast math).
Saves massive amounts of power compared to traditional methods.

They also showed that the system is robust. Even when they simplified the math or reduced the data quality, the "smart firecracker" neurons kept working well, proving that this approach is a strong candidate for building future, battery-friendly AI devices.

Technical Summary: Energy-Efficient Implementation of Spiking Recurrent Cells on FPGA

Problem Statement
Spiking Neural Networks (SNNs) offer a promising low-power alternative to conventional Artificial Neural Networks (ANNs) by leveraging sparse, event-driven computation. However, a significant trade-off exists between biological plausibility and hardware efficiency. Biologically faithful models are often too computationally expensive for Field-Programmable Gate Arrays (FPGAs), while standard simplified models like Leaky Integrate-and-Fire (LIF) or Integrate-and-Fire (IF) sacrifice complex neuronal dynamics, such as refractory periods and continuous state evolution, to achieve hardware feasibility. Furthermore, existing FPGA implementations often rely on online learning or specific architectures that limit flexibility. The challenge is to implement a neuron model that retains richer dynamics than LIF/IF models while remaining compatible with efficient, resource-constrained FPGA hardware.

Methodology
The authors propose an FPGA accelerator for an SNN utilizing Spiking Recurrent Cell (SRC) neurons. SRCs are derived from recurrent neural network (RNN) architectures and integrate spiking behavior directly into their dynamics, eliminating the need for an explicit reset mechanism common in LIF models.

To enable efficient FPGA implementation, the authors introduced a series of mathematical simplifications to the original SRC equations:

Fixed-Point Arithmetic: All variables and parameters were scaled by a factor of 1,000 and converted to integers (11-bit representation), eliminating costly floating-point operations.
Operator Simplification: The hyperbolic tangent (tanh) function was replaced with a piecewise linear approximation (Stanh) with a slope of 0.75. Multiplications by constants (e.g., 0.75) were implemented using bit-shift operations.
Thresholding Non-Linearities: The complex exponential function used to calculate the refractory switch variable $z_s[t]$ was replaced by a simple threshold rule. If the membrane potential exceeds a threshold $V_{th}$ , $z_s[t]$ switches to a "deep" state; otherwise, it remains in a "hyperbolic" state.
Parameter Adjustment: The parameter $r_s$ was adjusted from -7 to -8 to allow for shift-based multiplication, and explicit parameters were factored out to merge operations.

The system was implemented in VHDL on an AMD Xilinx Artix-7 XC7A200T FPGA clocked at 100 MHz. The architecture consists of four layers: an input interface, a fully connected SRC layer (100 neurons), an IR (Integrate-and-Reset) integrator layer (10 neurons), and a comparator output. Weight matrices were computed offline using Julia and stored directly in LUT-registers without modification, testing the model's robustness.

Key Contributions

Hardware-Optimized SRC Model: The paper presents a novel set of simplifications that allow the complex SRC model to run on FPGAs without floating-point units or expensive unary operators, while preserving continuous neuronal dynamics.
Robustness Validation: The study demonstrates that weights trained on the original, unsimplified SRC model (in Julia) can be directly transferred to the simplified FPGA implementation with minimal accuracy loss, validating the model's robustness to quantization and equation simplification.
Energy-Accuracy Trade-off Analysis: The work systematically investigates the impact of reducing spiking trace length and quantizing synaptic weights (down to 4 bits) on energy consumption and recognition accuracy.
Modular Architecture: A layered, synchronous architecture using a "Binder" module for synchronization and "NetWorkLevel" modules for parallel processing is proposed, facilitating reconfiguration and scalability.

Experimental Results
The system was evaluated using the MNIST dataset, converted into spiking traces (sequences of binary images).

Baseline Performance: With a 220-image spiking trace and 9-bit weights, the FPGA implementation achieved 96.31% accuracy with a processing time of 1.7424 ms per digit. This matched the accuracy of the simplified "Pseudo-VHDL" (PsV) simulation in Julia.
Energy Efficiency: By reducing the spiking trace length to 55 images and quantizing weights to 5 bits, the system achieved 93.32% accuracy at 0.55 mJ per digit. Further reduction to 44 images and 4-bit weights yielded 92.89% accuracy at 0.45 mJ per digit.
Resource Utilization: Reducing weight bit-width from 9 to 4 bits resulted in a 5–6% reduction in LUT usage per SRC neuron. The use of DSP48 units for SRC computations and full parallelization within layers contributed to low processing times.
Comparison: When compared to other FPGA-based SNN implementations (e.g., Carpegna et al., Han et al.), the SRC approach demonstrated competitive accuracy with significantly lower energy consumption per digit, particularly for short spiking traces. The authors note a smaller gap between training and test accuracy (1.1%) compared to other works, attributing this to the robustness of the SRC model.

Significance and Claims
The paper claims that SRC-based SNNs can deliver competitive performance with reduced energy consumption while preserving richer neuronal dynamics than standard LIF/IR models. The authors emphasize that the proposed simplifications allow for a trade-off between biological plausibility and hardware cost, making SRCs strong candidates for energy-efficient SNN accelerators.

The work highlights that increasing the parameter $z_{hyp}^s$ can reduce spike generation frequency by a factor of approximately three without significantly degrading accuracy, suggesting potential for event-driven scheduling in sparse activity regimes. The authors conclude that the combination of mathematical simplification, weight quantization, and trace length reduction offers a practical pathway to deploying complex SNNs on resource-constrained hardware, though they modestly note that future work is needed to explore adaptive event-driven scheduling and automation for larger networks.

Technical Summary: Energy-Efficient Implementation of Spiking Recurrent Cells on FPGA

More like this