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On-chip 1 TOPS Hyperdimensional Photonic Tensor Core using a WDM Silicon Photonic Coherent Crossbar

This paper presents an on-chip 0.96 TOPS hyperdimensional photonic tensor core utilizing a time-space-wavelength multiplexed silicon photonic crossbar that achieves high-speed tensor-vector multiplication with low error and demonstrates effective AI classification performance while offering a scalable path toward POPS-level computational throughput.

Original authors: S. Kovaios, I. Roumpos, A. Tsakyridis, M. Moralis-Pegios, D. Lazovsky, K. Vyrsokinos, N. Pleros

Published 2026-05-14

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CC BY 4.0

Original authors: S. Kovaios, I. Roumpos, A. Tsakyridis, M. Moralis-Pegios, D. Lazovsky, K. Vyrsokinos, N. Pleros

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to solve a massive, complex math puzzle. In the world of artificial intelligence (AI), these puzzles involve multiplying huge grids of numbers (matrices) by lists of numbers (vectors). Doing this with traditional electronic computers is like trying to carry all the water in a swimming pool one cup at a time: it works, but it's slow and uses a lot of energy.

This paper introduces a new, super-fast "photonic" (light-based) engine designed to solve these puzzles instantly. Here is how they did it, explained simply:

The Problem: Too Much Data, Too Little Space

Think of a standard computer chip as a small kitchen. If you try to cook a feast for a thousand people (a huge AI model) in that small kitchen, you run out of counter space and burn out the stove. The researchers wanted to build a "kitchen" that could handle massive amounts of data without running out of space or energy.

The Solution: A Three-Dimensional Highway

The team built a special "Crossbar" (a grid of roads for light) that uses three different tricks to move data at the same time. They call this TSWDM (Time-Space-Wavelength Division Multiplexing).

Space (The Road Lanes): Imagine a highway with multiple lanes. Instead of one car (data) driving down one road, they built a grid with many lanes side-by-side. This is the "Space" part.
Time (The Traffic Flow): Imagine those lanes are so busy that cars are driving in a continuous stream, one right after another, like a conveyor belt. They organize the math problems so they happen in rapid-fire succession. This is the "Time" part.
Wavelength (The Color Coding): This is the cleverest part. Imagine that instead of just using white light, they use different colors of light (like red, blue, green, and yellow) to carry different data streams simultaneously on the same road. Each color acts like a separate channel. This is the "Wavelength" part.

By combining these three, they created a "Hyperdimensional" engine. It's like having a highway where cars drive in multiple lanes, in a continuous stream, and each lane is painted a different color, all carrying different parts of the math puzzle at once.

The Experiment: The "Iris" Test

To prove this new engine works, they built a tiny silicon chip (about the size of a fingernail, 2 square millimeters) that acts as a 4-lane, 2-input version of this system.

The Speed: They ran data through it at incredibly high speeds (up to 60 billion symbols per second).
The Math Test: They asked the chip to perform "Tensor-Vector Multiplications" (a complex type of math). The chip got the answer right 96% of the time, with an average error of only 3.9%.
The Real-World Test: They used the chip to classify flowers (the famous "Iris dataset"). The chip correctly identified the type of flower 93.3% of the time when running at moderate speeds, and still managed 83.3% accuracy even when they pushed the speed to the maximum limit.

Why This Matters (The "Scalability" Secret)

The paper argues that this "Color Coding" (Wavelength) trick is the key to the future.

Imagine you want to build a bigger version of this chip to handle even bigger AI models.

The Old Way (Space only): To get more power, you would have to make the chip physically huge, adding more lanes. But as the chip gets bigger, the light gets dimmer and the math gets messier (more errors), requiring a super-powerful laser to push the light through.
The New Way (Wavelength): By adding more colors instead of just making the chip physically wider, they can boost the power without needing a massive laser. It's like adding more radio stations to the same frequency band rather than building a new tower.

The Bottom Line

The researchers demonstrated a working prototype that can perform 0.96 TOPS (Tera Operations Per Second) of computing power on a tiny chip. They predict that if they scale this up using their "color coding" method, they could eventually build photonic accelerators capable of 491.5 TOPS (nearly 500 times faster than their current prototype) while using less energy and laser power than traditional methods.

In short, they built a light-speed math engine that uses space, time, and color to solve AI problems faster and more efficiently than ever before, proving it works on a real-world flower classification task.

Technical Summary: On-chip 1 TOPS Hyperdimensional Photonic Tensor Core using a WDM Silicon Photonic Coherent Crossbar

Problem Statement
The rapid expansion of artificial intelligence (AI) applications has created an urgent demand for computing systems capable of performing highly efficient linear algebra operations, specifically matrix-vector (MVM) and tensor-vector (TVM) multiplications. While photonic accelerators offer promising energy efficiency and bandwidth, current implementations face significant hurdles in scaling to meet the parameter requirements of modern AI models. Existing approaches often rely on single multiplexing dimensions: Space Division Multiplexing (SDM) via coherent photonic meshes suffers from insertion losses that limit scalability; Wavelength Division Multiplexing (WDM) faces challenges in generating substantial channel counts on-chip; and Time Division Multiplexing (TDM) introduces latency and leaves throughput scaling unresolved. Furthermore, state-of-the-art experimental demonstrations exceeding hundreds of TOPS have largely relied on bulk fiber-based devices, leaving on-chip systems struggling to simultaneously employ time, space, and wavelength multiplexing.

Methodology
The authors propose and experimentally validate a novel Time-Space-Wavelength Division Multiplexing (TSWDM) Xbar architecture. This design generalizes the coherent photonic Crossbar (Xbar) to support three simultaneous multiplexing dimensions:

Time: Operations are serialized over the time domain.
Space: Computational workload is distributed across spatial rows and columns.
Wavelength: Elementary computational nodes are parallelized across multiple wavelength channels.

The architecture consists of a multiwavelength source, an $L \times M \times N$ Xbar mesh (where $L$ , $M$ , and $N$ represent wavelength channels, rows, and columns), and a demultiplexing detection site. The system utilizes a grid of multiplexed computational nodes, where each node comprises an array of elementary elements (typically an amplitude modulator and a phase modulator) interleaved between demultiplexing and multiplexing stages.

For experimental validation, the authors fabricated a 4-channel, 2-input silicon photonic Xbar on a 200 mm IMEC platform. The chip integrates:

SiGe 50 $\mu$ m, 56 GHz Franz-Keldysh Electro-Absorption Modulators (EAMs) serving as input and weight modulators.
170 $\mu$ m Thermo-Optical Phase Shifters (TO-PS) to ensure proper sign imprinting and constructive interference.
On-chip 4-channel dual-microring (DE)-MUX stages providing 3 nm adjacent channel spacing.

The experimental setup employed a 4-channel tunable laser source, an arbitrary waveform generator (AWG) for RF driving, and offline implementation of the temporal integrator and activation functions. The system was tested for DC characterization, Tensor-Vector multiplication (TVM), and inference on a fully connected neural network trained for the Iris dataset classification.

Key Results

Tensor-Vector Multiplication: The 4-channel, 2-input TSWDM Xbar successfully demonstrated TVM operations with an average error of 3.9% compared to ideal products. This was achieved by calibrating the system to restore non-linearity and non-uniform insertion losses (IL) of the modulators.
Neural Network Inference: In the Iris dataset classification task, the photonic processor achieved an experimental accuracy of 93.3% at data rates between 4 $\times$ 10 and 4 $\times$ 30 GBd. Accuracy remained robust, reaching 83.3% even when the data rate increased to 4 $\times$ 60 GBd.
Computational Throughput: The on-chip system demonstrated a computational throughput of 0.96 TOPS with a footprint efficiency of 480 GOPS/mm².
Scalability Analysis: Theoretical analysis indicates that incorporating a WDM scheme into the SDM architecture reduces the required operating laser power. For a specific computational throughput, the WDM approach offers up to a 1-bit improvement in achievable bit resolution compared to a pure SDM Xbar of equivalent power, primarily due to reduced insertion losses associated with fewer physical crossings in scaled-up layouts.

Significance and Claims
The paper claims to present the first coherent hyper-multiplexed photonic processor capable of performing arbitrary MVM and TVM computations on-chip by synergizing time, space, and wavelength dimensions. The authors assert that this architecture provides a mature path to scale computational power while supporting a large number of trainable parameters, addressing the limitations of single-dimension multiplexing schemes.

The work highlights that while spatial and spectral dimensions are interchangeable in terms of raw computational power, the WDM approach offers a more sustainable route for scaling photonic circuits. Specifically, the analysis suggests that WDM layouts can feasibly boost the potential for constructing photonic accelerators with computational throughput in the POPS (Peta-Operations Per Second) regime by reducing laser power requirements and mitigating the insertion loss penalties associated with increasing spatial dimensions. The experimental demonstration of a 0.96 TOPS on-chip core serves as a proof-of-concept for this hyperdimensional approach.

The Problem: Too Much Data, Too Little Space

The Solution: A Three-Dimensional Highway

The Experiment: The "Iris" Test

Why This Matters (The "Scalability" Secret)

The Bottom Line

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