Technical Summary: Loaded Dice: Solving the Non-Selection Problem for Scalable Probabilistic RowHammer Defense

1. Problem Statement

The RowHammer vulnerability, where repeated activation of DRAM rows induces bit flips in adjacent victim rows, has become increasingly severe as DRAM technology scales. The minimum number of activations required to induce a flip (the RowHammer threshold, $T_{RH}$) has dropped significantly, particularly for double-sided attacks ($T_{RH-D}$).

Existing mitigation strategies face a trade-off between security, performance, and area overhead:

• Per Row Activation Counting (PRAC): Standardized for DDR5, PRAC uses per-row counters to track activations precisely. However, updating these counters on every activation via read-modify-write operations significantly increases DRAM timing parameters (e.g., $t_{RP}$ and $t_{RC}$), leading to substantial performance degradation (e.g., ~14% average slowdown) and notable area overhead due to counter cells.
• Probabilistic Mitigations (e.g., MINT): These schemes avoid per-row counters by randomly selecting rows for mitigation within periodic windows. While effective at high thresholds ($T_{RH-D} \ge 1000$), they suffer from the non-selection problem at lower thresholds. To ensure a heavily hammered row is not repeatedly skipped by random sampling, these schemes must statically increase their mitigation rate (issuing Refresh Management commands, RFMs, more frequently). This fixed-rate scaling reduces effective memory bandwidth and causes significant slowdowns (e.g., 17.5% at $T_{RH-D}=250$) even when no attack is present.

The core challenge is to design a mitigation that scales to low $T_{RH-D}$ without uniformly increasing the mitigation frequency, thereby preserving performance for benign workloads while maintaining security.

2. Methodology: PrISM

The authors propose PrISM (Probabilistic Intersection-based Sampling Mitigation), a scalable in-DRAM defense that correlates sampled row addresses across mitigation windows to address the non-selection problem.

Core Mechanism

PrISM operates on fixed-size mitigation windows but utilizes a Sampled History Queue (SHQ) to track row activity over time.

1. Sampling: In each window, PrISM randomly samples $R$ activation slots out of $W$ total slots.
2. Intersection Detection: When a row is sampled, PrISM checks if it matches any entry in the SHQ, which stores sampled-but-unmitigated rows from the previous $L$ windows (the lookback window).
3. Mitigation Request:
   • Default Mitigation: One non-intersecting sampled row is selected as the default mitigation candidate for the window.
   • Additional Mitigation: If a sampled row matches an entry in the SHQ (an "intersection"), it indicates persistent activity. PrISM enqueues this row into a Pending Mitigation Queue (PMQ) and requests an additional mitigation via the existing JEDEC Alert Back-Off (ABO) protocol.
4. Service: The PMQ buffers rows awaiting service. Rows are mitigated during default opportunities (Target Row Refresh or proactive RFMs). If the PMQ fills up or a row's activation count exceeds a tardiness threshold ($T_{PMQ}$), PrISM asserts an Alert to trigger an immediate RFM.

Key Design Features

• No Per-Row Counters: PrISM avoids the area and timing overhead of PRAC by not maintaining counters for every row.
• Dynamic Mitigation Rate: Unlike MINT, which increases the mitigation rate globally as $T_{RH-D}$ drops, PrISM keeps the default mitigation rate low. It only increases mitigation frequency when persistent activity (intersections) is detected.
• JEDEC Compatibility: PrISM reuses the existing ABO protocol and requires no changes to the DRAM array or interface.
• Address Mapping: For ultra-low thresholds ($T_{RH-D} \le 250$), PrISM employs randomized address mapping to prevent benign workloads with high spatial locality from triggering false intersections.

3. Key Contributions

• Identification of the Non-Selection Problem: The paper identifies the statistical barrier where fixed-rate probabilistic defenses fail at low thresholds, necessitating a new approach that does not rely on uniform rate scaling.
• PrISM Design: A novel intersection-based mitigation that uses an SHQ to correlate sampled rows across windows, enabling targeted additional mitigations only for persistent aggressors.
• Security Analysis: The authors model a worst-case "Circular-X-Rows" attack to determine the minimum supported $T_{RH-D}$ for various configurations of window size ($W$), sampled slots ($R$), and lookback window ($L$).
• Comprehensive Evaluation: The paper evaluates PrISM against PRAC (specifically QPRAC) and MINT across 57 workloads, varying $T_{RH-D}$, memory intensity, and system configurations.

4. Results

The evaluation, conducted using the Ramulator2 DRAM simulator with an 8-core OoO processor and DDR5-8000B, demonstrates the following:

• Performance Overhead:
  • At $T_{RH-D} = 500$, PrISM incurs a negligible 0.2% average slowdown, compared to 14% for PRAC and 7.1% for MINT.
  • At the ultra-low threshold of $T_{RH-D} = 250$, PrISM achieves a 1.5% average slowdown. In contrast, MINT suffers a 10.7% slowdown, and PRAC remains at ~14%.
  • On high-memory-intensity workloads, PrISM reduces slowdown from 17.5% (MINT at $T_{RH-D}=250$) to 2.5%.
• Storage Overhead:
  • PrISM requires only 625B of SRAM per bank at $T_{RH-D}=500$.
  • This is 20× smaller than Mithril and 170× smaller than ProTRR at the same threshold. Even at $T_{RH-D}=250$, PrISM's storage is one to two orders of magnitude lower than secure counter-based defenses.
• Power Overhead:
  • Power overhead is minimal, estimated at roughly 0.6% to 1.0% of total DRAM chip power, primarily due to the SRAM structures and a small TRNG.
• Security:
  • PrISM supports $T_{RH-D}$ down to 250 with a target Mean-Time-to-Failure (MTTF) of 10,000 years per bank.
  • The system is robust against Denial-of-Service (DoS) attacks; while an attacker can force worst-case slowdowns (up to 2.31× at $T_{RH-D}=250$), this is comparable to existing memory performance attacks.

5. Significance and Claims

The paper claims that PrISM represents a significant advancement in RowHammer defense by resolving the scalability limitations of probabilistic schemes without incurring the high costs of deterministic counter-based approaches.

• Scalability: PrISM successfully scales to low $T_{RH-D}$ (down to 250) by dynamically increasing mitigation only when necessary, avoiding the "fixed-rate scaling" penalty of prior probabilistic methods.
• Practicality: By reusing the existing ABO protocol and requiring no DRAM array modifications, PrISM is presented as a practical solution for near-term DDR5 systems where PRAC adoption is uncertain due to its high overhead.
• Efficiency: The combination of negligible performance slowdown, minimal storage requirements, and low power consumption positions PrISM as a superior alternative to both PRAC and existing probabilistic defenses like MINT, particularly for high-performance, memory-intensive workloads.

The authors conclude that PrISM provides secure RowHammer protection with performance and area characteristics that make it viable for commercial deployment in current and future DRAM technologies.