Breaking the width-scaling limit in high-performance atomically thin 2D nanoribbon transistors

This paper demonstrates that ultra-scaled monolayer and bilayer molybdenum disulfide nanoribbon transistors can overcome the conventional width-scaling bottleneck by achieving enhanced on-current density and superior electrostatic control at channel widths as narrow as 15 nm.

The Gist

The Big Problem: The "Traffic Jam" at the Edges

Imagine a highway (a computer transistor) where cars (electrons) drive from point A to point B to do work. For decades, engineers have made these highways shorter and thinner to fit more of them on a single chip, making computers faster and more efficient.

However, they hit a wall. While they could make the highway very short, they couldn't make it very narrow without causing a traffic jam.

• The Old Rule: If you make a road too narrow (below 50 nanometers), the edges become rough and messy. Cars crash into the sides, slow down, or get stuck. This is called "edge disorder."
• The Result: In normal materials (like silicon), making the road narrower actually makes the traffic worse. The current (flow of cars) drops, and the device performs poorly. This is known as the "width-scaling wall."

The New Discovery: The "Super-Highway" Effect

The researchers at Chalmers University of Technology discovered that if you use a very special, ultra-thin material called Molybdenum Disulfide (MoS₂)—which is only one or two atoms thick—you can break this rule.

Instead of a traffic jam, making the road narrower actually makes the traffic flow faster.

How They Did It: The "Laser-Cut" Technique

To make these tiny roads, the team had to be incredibly precise.

1. The Material: They started with a sheet of MoS₂, which is like a sheet of paper so thin it's invisible to the naked eye.
2. The Cutting: They used a high-tech "laser" (electron beam) to draw the shape of the road and then etched away the rest.
3. The Secret Sauce: They used a very thin layer of protective coating and a special gas shield (argon) while cutting. This ensured the edges of the road were perfectly smooth and sharp, rather than jagged and messy.

The Surprising Results

They tested these "nanoribbons" (the tiny roads) at different widths, going all the way down to 15 nanometers (which is about 10,000 times thinner than a human hair).

• The "Sweet Spot" (30–80 nm): As they made the roads narrower, the traffic didn't slow down; it sped up!

  • For the single-layer roads, the traffic flow (current) increased by 230%.
  • For the double-layer roads, it increased by 170%.
  • Analogy: Imagine a narrow hallway where, instead of people bumping into the walls, the walls actually push the people forward, making them run faster.

• The "Ultra-Narrow" Limit (15 nm): When they went even narrower (down to 15 nm), the traffic flow stopped increasing and leveled off (saturated). It didn't get worse, but it didn't get better either. This suggests they found the absolute smallest size possible for this material before the physics changes again.

Why Is This Important?

In the world of computer chips, this is a game-changer because of two main reasons:

1. More Power in Less Space: Usually, to get a computer chip to do more work, you need to make the roads wider. But with this new discovery, you can make the roads narrower and get more power. This means you can fit many more transistors on a chip without them overheating or slowing down.
2. Better Control: The researchers found that the "gate" (the switch that turns the traffic on and off) works much better on these narrow roads. The switch is sharper, and the traffic stops and starts more cleanly, which saves energy.

The Bottom Line

This paper proves that for a specific type of ultra-thin material (MoS₂), the old rule "narrower is worse" is wrong. By using a precise cutting technique, they created the world's narrowest transistor channels that actually perform better than wider ones. This opens the door to building the next generation of super-fast, energy-efficient computers that are much smaller than anything we have today.

Technical Summary

Technical Summary: Breaking the Width-Scaling Limit in High-Performance Atomically Thin 2D Nanoribbon Transistors

Problem Statement
While state-of-the-art transistor technology has successfully scaled gate lengths and channel thicknesses down to the 5 nm regime, channel width scaling has encountered a "width-scaling wall" at approximately 40–50 nm. In conventional semiconductors, reducing channel width below this threshold typically leads to performance degradation due to dangling bonds, edge disorder, and lateral depletion. These factors suppress drive current, degrade mobility, and increase the sub-threshold swing. Consequently, p-type MOSFETs require significantly wider channels than n-type devices to compensate for lower hole mobility, further limiting CMOS integration density. Although two-dimensional semiconductors (2DSCs) like molybdenum disulfide (MoS₂) offer atomically thin channels with immunity to short-channel effects, previous demonstrations of narrow 2DSC nanoribbons have largely relied on micrometer-wide channels or exhibited degraded electrical performance when scaled down, reinforcing the assumption that edge scattering and depletion are unavoidable bottlenecks.

Methodology
To address these challenges, the authors developed an optimized top-down fabrication process to create high-quality, atomically sharp monolayer and bilayer MoS₂ nanoribbons with controlled widths down to 15 nm. The fabrication strategy focused on two critical parameters to minimize process-induced damage and edge disorder:

1. Resist Optimization: The electron-beam resist thickness was reduced to approximately 50–60 nm. This minimizes forward scattering and the lateral spread of secondary electrons, allowing for a balanced height-to-width aspect ratio in the exposed nanopatterns.
2. Etching Technique: Anisotropic inductively coupled plasma (ICP) etching was employed using a trifluoromethane (CHF₃)/argon (Ar) gas mixture. Crucially, argon-mediated sidewall protection was utilized to suppress lateral undercut and preserve edge fidelity, preventing the formation of damaged or disordered edges.

The resulting devices were back-gated transistors fabricated on SiO₂/Si++ substrates with Ni/Au source and drain contacts. The structural integrity of the nanoribbons was verified using Raman spectroscopy, confirming that the patterning process preserved the crystallinity and edge quality of the material.

Key Results
The study demonstrates a counter-intuitive "edge-enhanced transport regime" where reducing the channel width of MoS₂ nanoribbons leads to enhanced device performance, directly contradicting the degradation trends observed in conventional semiconductors.

• Monolayer MoS₂: As the channel width was reduced from 50 nm to 30 nm, the on-current density increased monotonically from 35 µA/µm to 110 µA/µm (an enhancement of up to 230%). The devices maintained high on/off ratios (10⁶) and improved field-effect mobility.
• Bilayer MoS₂: A similar trend was observed in bilayer devices. Reducing the width from 80 nm to 30 nm resulted in an on-current density increase from ~125 µA/µm to ~300 µA/µm (an enhancement of up to 170%). At 30 nm width, the bilayer devices achieved current densities comparable to or exceeding state-of-the-art few-layer MoS₂ transistors with much wider channels.
• Ultra-Scaled Regime (15 nm): The authors successfully scaled bilayer MoS₂ nanoribbons down to 15 nm. In this ultra-narrow regime, the on-current density saturated at approximately 200–300 µA/µm. While the continuous enhancement observed between 80 nm and 30 nm leveled off, the devices did not suffer the catastrophic performance collapse typically expected at this scale. The 15 nm devices retained high on/off ratios (>10⁶) and stable threshold voltages.
• Mechanism: The performance enhancement is attributed to "electrostatic edge enhancement." As the lateral dimension decreases, the gate field couples more efficiently into the channel, overcoming edge scattering and carrier depletion. The electron mean free path (~5 nm) is significantly shorter than the nanoribbon width, suggesting that edge scattering plays a negligible role in the 30–80 nm range.

Significance and Claims
The paper claims to have broken the "width-scaling wall" for 2D semiconductor nanoribbons, establishing a new dimensional scaling rule where performance improves with decreasing width down to 30 nm, followed by a saturation regime at 15 nm rather than degradation.

The authors assert that these findings provide an experimental foundation for the ultimate scaling of transistor technologies. By demonstrating that atomically thin nanoribbons can maintain or enhance drive current density at widths as narrow as 15 nm, the work suggests a pathway to higher-density, lower-power logic circuits. Specifically, achieving target drive currents with less total channel width could reduce gate capacitance and dynamic switching energy. The study positions 2DSC nanoribbons as a promising architecture for overcoming the integration density limits imposed by the width-scaling constraints of current silicon-based technologies.