🤖 machine learning

Uncertainty-Aware End-to-End Co-Design of Neural Network Processors: From Training and Mapping to Fabrication

This paper presents a unified, uncertainty-aware co-design framework that integrates neural network training, hardware mapping, and fabrication into interoperable blocks, introducing "Confidence" as an explicit optimizable resource to enable modular improvements and automatically propagate global Pareto-optimal solutions across the entire design pipeline.

Original authors: Yuyang Du, Yujun Huang, Gioele Zardini

Published 2026-06-04

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Yuyang Du, Yujun Huang, Gioele Zardini

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to build a custom robot that needs to be fast, cheap, and reliable. In the past, building such a machine was like trying to assemble a puzzle where the pieces were made by three different people who never talked to each other.

Person A designed the robot's "brain" (the neural network software).
Person B built the robot's "body" (the computer chip).
Person C ran the factory to manufacture the chips.

The problem was that Person A didn't know how Person B's design would affect the factory's success rate. Person B didn't know if Person A's brain was too complex for the factory to produce. They made decisions in separate silos, often leading to expensive mistakes or designs that couldn't be built at all.

This paper introduces a new way to design these systems called "Uncertainty-Aware End-to-End Co-Design." Think of it as a universal translator and project manager that brings all three people into the same room to solve the puzzle together, while also accounting for the fact that the future is uncertain.

Here is how the paper breaks it down using simple analogies:

1. The "Black Box" Approach (The Modular System)

The authors created a framework made of four distinct "blocks" that talk to each other, but only through a specific set of rules.

Block 1 (Training): Decides what the brain looks like and how long to study.
Block 2 (Mapping): Decides how to fit that brain onto a chip.
Block 3 (Fabrication): Predicts how many working chips the factory will actually produce.
Block 4 (Resources): Manages the budget for time, money, and electricity.

The Magic Trick: Each block is like a sealed black box. The system only cares about what goes in (resources like money and time) and what comes out (functionality like speed and accuracy). It doesn't care how the box does its job.

Why this matters: If you want to upgrade the "Training" box with a smarter algorithm, you can swap it out without breaking the "Factory" box. You don't have to rebuild the whole system every time you improve one part.

2. The "Confidence" Currency

Usually, engineers try to guess the future with a single number (e.g., "This chip will cost $10"). But in reality, things are messy. Training a brain is like rolling dice; manufacturing chips has random defects.

This paper introduces a new currency called Confidence.

Instead of asking, "Can we make this chip?" (Yes/No), the system asks, "How much extra money and time are you willing to spend to be 99% sure we can make it?"
The Analogy: Imagine buying a lottery ticket.
- Low Confidence: You spend $1 and have a 10% chance of winning.
- High Confidence: You spend $100 to guarantee a win.
- The framework treats "Confidence" just like "Money" or "Time." It lets you see the trade-off: "If I want to be 99% sure my robot works, I need to spend 20% more time training it."

3. The "Surrogate" Shortcut

Designing these systems usually requires running massive, slow simulations for every single idea. That takes forever.

The Paper's Solution: They use surrogates. Think of these as "crystal balls" or "predictive maps" trained on past data.
Instead of running a full factory simulation for every idea, the system looks at the map and says, "Based on what we've seen before, this design will likely cost $X and work Y% of the time."
This makes the whole process incredibly fast, allowing the system to test thousands of combinations in seconds.

4. Real-World Tests (The Case Studies)

The authors tested their system with three scenarios to prove it works:

Test 1 (The Baseline): They designed a robot for cleaning indoor spaces. The system found the perfect balance between cost and power, showing that you can't just minimize one thing without hurting the other.
Test 2 (The Tight Constraints): They tried to design a robot for a tiny hearing aid (very small size, very low battery). They showed that as you make the rules stricter, the "Confidence" knob becomes crucial. You can choose to accept a lower chance of success to save money, or pay more to be absolutely sure it works.
Test 3 (The Upgrade): They improved just one part of the system (the chip design solver). Because of their "black box" design, the improvement automatically made the entire system better without them having to touch the other three blocks.

Summary

In short, this paper proposes a smart, modular assembly line for building AI chips.

It connects the software, hardware, and factory into one loop.
It treats reliability as a budget item you can trade off against cost and time.
It uses predictive shortcuts to find the best designs quickly.
It allows engineers to upgrade individual parts without breaking the whole machine.

The result is a way to build better, more reliable, and more cost-effective AI processors by acknowledging that the future is uncertain and planning for it from day one.

Technical Summary: Uncertainty-Aware End-to-End Co-Design of Neural Network Processors

Problem Statement
Designing a Neural Network Processor (NNP) is inherently an end-to-end co-design problem involving four interdependent stages: network architecture and training, hardware mapping, wafer-level fabrication, and compute resource allocation. Decisions in early stages (e.g., training budget) dictate the inference workload, while hardware mapping determines chip area, latency, and energy, which subsequently influence fabrication yield and manufacturing cost.

Current methodologies suffer from three primary limitations:

Lack of Modularity: Existing approaches (e.g., Hardware-Aware NAS, joint exploration tools like NAAS or DANCE) tightly couple the global objective to specific search algorithms. Improving one component (e.g., a training surrogate) often requires reworking the entire exploration pipeline.
Evaluation Cost: Exhaustive exploration across network, mapping, and manufacturing choices is infeasible due to the high cost of detailed hardware verification, forcing reliance on standalone statistical predictors rather than a composable framework.
Handling Uncertainty: Stochastic elements in training (random initialization), mapping (heuristic search), and fabrication (process variation) are typically collapsed into point estimates or treated as nuisance variables, rather than being explicitly managed as optimizable resources.

Methodology
The paper proposes a unified framework grounded in Monotone Co-Design Theory. The core innovation is the decomposition of the NNP design process into four interoperable Monotone Design Problems with Implementation (MDPIs). Each block exposes only a functionality–resource interface to the rest of the system, hiding its internal algorithmic details.

The four MDPI blocks are:

Network Selection and Training Pipeline: Maps training budgets to embedding configurations and accuracy guarantees.
Chip Design Pipeline: Maps embedding configurations and solver budgets to chip-level Area, Energy, and Latency (LEA).
Fabrication Prediction: Maps chip area and monetary cost to the number of yielded functional chips.
Computation Distribution Planner: Allocates computational budgets (time, power, cost) between the training and mapping blocks.

Key Contributions

Formal Composition via MDPIs:
The framework treats each subsystem as an MDPI, defined by a set of implementations and a map to a Design Problem (DP) over functionality and resource posets. This allows the system to be composed using series, parallel, and feedback operations. Crucially, the internal solver (e.g., a Genetic Algorithm for mapping) is opaque; only the resulting set of feasible functionality-resource pairs is visible. This ensures that improving a single block's implementation set does not require structural changes to the global co-design diagram.
Uncertainty as a First-Class Resource (Confidence):
The paper extends MDPIs to handle distributional uncertainty. Instead of collapsing stochastic outcomes into point estimates, the framework introduces Confidence ( $\pi^{-1}$ ), the inverse of the success probability, as an explicit, optimizable resource alongside cost, time, and power.
- Training: Modeled as a budgeted stochastic process where accuracy follows a learning curve with homoscedastic Gaussian noise.
- Mapping: Modeled using a surrogate distribution (a three-component mixture model) over LEA metrics derived from Genetic Algorithm runs.
- Fabrication: Modeled using a negative binomial yield model to account for defect clustering, mapping area and cost to a distribution of yielded chips.
  The global confidence is the product of component confidences (under independence assumptions), allowing designers to trade off reliability against resource expenditure.
Surrogate-Based Evaluation:
To address evaluation costs, the framework relies on offline-profiled surrogates (e.g., Gaussian learning curves, mixture distributions for LEA, and negative binomial yield models). These surrogates allow the system to compute Pareto-optimal solutions in seconds without re-invoking expensive underlying solvers.

Results
The framework is validated through three case studies:

Case Study I (End-to-End Co-Design): Solves a baseline NNP design problem for an indoor cleaning robot. The solver recovers Pareto-optimal implementations spanning network architecture, mapping strategy, fabrication node, and compute hardware. It demonstrates that the framework can identify non-intuitive trade-offs (e.g., aggressive hardware choices reducing cost at the expense of power) that sequential optimization would miss.
Case Study II (Multi-Scenario & Uncertainty):
- Constraint Sensitivity: Evaluates four scenarios with progressively tighter constraints (Area, Energy, Latency, Yield, Accuracy). Results show a monotonic outward shift of the Pareto boundary as constraints tighten, consistent with the order-theoretic structure of the formalism.
- Confidence as a Design Knob: Demonstrates that Confidence functions as a continuously tunable resource. For a highly constrained scenario (neural implant), the Time–Confidence Pareto front reveals a steep trade-off: achieving high reliability requires disproportionate time investment. This quantifies the "cost of reliability," a metric hidden in deterministic formulations.
- Surrogate Validation: Validates that the surrogate distributions for training, mapping, and fabrication faithfully capture observed stochasticity, justifying the use of Confidence as a reliable design resource.
Case Study III (Algorithm–Framework Decoupling): Validates modularity by enriching the implementation set of the Chip Design block (simulating a better solver by increasing GA epochs). The results show that improvements in a single block automatically propagate to the global Pareto front without modifying the co-design diagram or other blocks. Dominated implementations are pruned automatically, while non-dominated improvements shift the global front.

Significance
The paper claims that this formalism provides a foundation for principled, end-to-end NNP co-design that simultaneously offers:

Compositionality: The ability to compose designs across abstraction levels (training to fabrication).
First-Class Uncertainty Quantification: Treating reliability as a tunable design knob rather than a post-hoc diagnostic.
Modularity: Allowing algorithmic improvements in any single block to be contributed and composed independently, fundamentally changing the economics of iterative NNP development.
Evaluation Efficiency: Enabling rapid exploration via offline surrogates without sacrificing the ability to model stochasticity.

The authors position this work as a step toward a rigorous, flexible, and modular methodology that bridges the gap between high-level co-design exploration and tape-out-ready implementation, distinct from prior joint-search methods that lack formal compositional guarantees.