💻 computer science

FP8 is All You Need (Part 1): Debunking Hardware FP64 as the HPC Holy Grail

This paper argues that native hardware FP64 is no longer essential for high-performance computing, demonstrating that AI-optimized GPUs like NVIDIA's B300 can achieve full FP64 accuracy and memory-bound performance through FP8 tensor throughput combined with the Ozaki Scheme II, thereby surpassing the capabilities of previous generations despite their reduced native double-precision silicon.

Original authors: Satoshi Matsuoka

Published 2026-06-08

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Satoshi Matsuoka

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

The Big Problem: The "High-Precision" Cliff

Imagine the world of supercomputers as a massive highway system designed to carry heavy trucks (scientific data). For decades, the rule was: "To carry these heavy trucks safely, you must use a specific, ultra-strong bridge called 'FP64' (Double Precision)."

However, the paper argues that the new generation of computer chips (specifically NVIDIA's "Blackwell Ultra" and "Rubin" GPUs) has decided to stop building these strong bridges. Instead, they are building thousands of tiny, incredibly fast lanes for "FP8" (a low-precision format used for AI).

The Old Way: The chip had a strong bridge (FP64) that could handle 40 tons of traffic.
The New Way (B300/Rubin): The chip removed the strong bridge entirely. It now has a tiny, wobbly footbridge (FP64) that can only handle 1.3 tons, while the massive AI lanes (FP8) can handle 5,000 tons.

The Result: If you try to run old scientific software on these new chips, the traffic jams up on the tiny footbridge. The massive AI lanes sit empty and useless. The paper calls this the "FP64 Cliff."

The Solution: The "Ozaki Scheme" (The Magic Translator)

The paper proposes a clever workaround. Instead of trying to build a new strong bridge, why not use the massive AI lanes to pretend they are a strong bridge?

This is where the Ozaki Scheme II comes in. Think of it as a Master Translator that uses a mathematical trick called the "Chinese Remainder Theorem."

The Analogy: Imagine you need to send a very long, complex secret message (a high-precision number) across a river, but the only boat available is small and can only carry short, simple notes.
The Trick: Instead of sending the whole message at once, the translator breaks the message into 10 or 12 tiny, simple notes (residues).
The Execution: It sends all 10 notes across the river simultaneously using the fast, wide AI lanes.
The Reassembly: On the other side, a quick math formula (Garner's algorithm) stitches the 10 notes back together into the original, perfect, high-precision message.

Because the "notes" are simple, the AI lanes can carry them at lightning speed. The paper claims that by doing this, you can get the speed of the AI lanes while keeping the accuracy of the old strong bridge.

The "Tensor-Memory Equilibrium" (The New Traffic Law)

The authors created a new model called the Tensor-Memory Equilibrium (TME) to prove this works.

The Old View: "If the bridge is weak, the whole system is slow."
The New View: "If the bridge is weak, but the road leading to it is wide enough, we can just keep the cars moving."

The paper shows that for most scientific tasks (like weather simulation or fluid dynamics), the bottleneck isn't the math; it's the memory bandwidth (how fast data can be loaded into the chip).

The Good News: The new chips have massive memory bandwidth.
The Catch: The old math units were too slow to use that bandwidth.
The Fix: The Ozaki Scheme uses the fast AI math units to process the data while it's being loaded. This allows the system to run at the speed of the memory bandwidth, not the speed of the weak bridge.

The Results: Speeding Up Without Losing Accuracy

The paper runs the numbers on the new chips (B300 and Rubin) and compares them to the previous generation (H100 and B200).

For "Heavy" Math (Dense Matrix Multiplication):
- Native FP64 on new chips: Extremely slow (1.3 TFLOPS).
- Ozaki Scheme on new chips: Super fast (500 TFLOPS).
- Result: The new chip is 380 times faster than its own native mode and 12 times faster than the previous generation's best chip.
For "Memory-Heavy" Tasks (Stencils, SpMV):
- These tasks are usually limited by how fast data can be read, not how fast it's calculated.
- Native FP64: Stuck at the speed of the weak bridge.
- Ozaki Scheme: Matches the speed of the massive memory bandwidth.
- Result: The new chip performs just as well as the old, "balanced" chips, but with much more raw power available for other things.

The "Four-Floor" Safety Net

The paper argues that to make this work for every type of scientific code, you need a "Four-Floor" building:

The FP8 Floor: The massive AI lanes (which the new chips have plenty of).
The INT32 Floor: A backup lane for specific math tricks (FFT).
The FP32 Floor: A standard lane for simple math.
The FP64 Floor: The old strong bridge.

The Paper's Conclusion: We don't need the 4th floor (native FP64) anymore. The first three floors, combined with the Ozaki Translator, are strong enough to hold the entire building.

The Catch: It Requires "Construction Work"

The paper admits that this isn't magic; it requires engineering.

You can't just plug in old software and expect it to work. You have to rewrite the "plumbing" (the kernel code) to use this translator.
The Silver Lining: The author argues that because AI coding assistants (like the ones used to write this paper) are so good at translating patterns, this "construction work" can be done in months, not years.

Summary

The paper claims that the era of needing "native" double-precision silicon (FP64) is over. Even though NVIDIA's newest chips have removed the hardware for it, we can use a mathematical trick (Ozaki Scheme) to turn their massive AI engines into perfect double-precision calculators.

The Bottom Line: You don't need the "Holy Grail" of FP64 silicon anymore. If you have enough FP8 power and the right software translator, FP8 is all you need to run the world's most complex scientific simulations.

Technical Summary: FP8 is All You Need (Part 1)

1. Problem Statement

The paper addresses a critical divergence in High-Performance Computing (HPC) hardware architecture. While scientific simulations (e.g., Quantum Chromodynamics, CFD, climate modeling) rely on IEEE 754 double-precision (fp64) arithmetic for numerical stability, modern data-center GPUs are pivoting toward low-precision AI workloads.

The NVIDIA Blackwell Ultra (B300) and the upcoming Rubin (R200) architectures exemplify this shift. The B300 delivers massive throughput in low-precision formats (10–15 PFLOPS in NVFP4/fp8) but has collapsed native fp64 tensor performance to approximately 1.3 TFLOPS—a 30× regression compared to the B200. This creates two specific pathologies:

Memory-Bound Kernels Become Compute-Bound: The "ridge point" (where compute and memory limits intersect) on B300 drops to 0.16 FLOPS/Byte. Consequently, standard memory-bound kernels like Sparse Matrix-Vector multiplication (SpMV), stencils, and batched GEMV, which previously ran at the memory bandwidth limit, are now artificially capped by the weak native fp64 arithmetic units.
Dormant Silicon: The massive low-precision tensor cores (fp8/NVFP4) remain idle during fp64-only HPC workloads, representing a "Dark Silicon" inefficiency.

The central question is whether native fp64 silicon remains the "holy grail" of HPC, or if abundant fp8 throughput combined with algorithmic emulation can restore full fp64 accuracy and performance.

2. Methodology and Analytic Model

The Tensor–Memory Equilibrium (TME) Model

The authors introduce the Tensor–Memory Equilibrium (TME) model, an extension of the classical Roofline model, to analyze the performance of emulated fp64 on low-precision hardware. The model introduces three emulation-specific parameters:

$\alpha$ (Compute Multiplier): The number of low-precision tensor-core operations required per high-precision operation (e.g., the number of moduli $r$ in the Chinese Remainder Theorem approach).
$\beta$ (Bandwidth Multiplier): The ratio of data movement in the emulated kernel versus the native kernel. Crucially, the paper argues that if decomposition and reconstruction are fused at the register level, $\beta$ can approach 1, meaning the emulation adds no global memory traffic overhead.
$\gamma$ (Reconstruction Latency): The latency cost of reconstructing the final result (e.g., via Garner's algorithm).

The Ozaki Scheme II

The paper utilizes the Ozaki Scheme II, a method based on the Chinese Remainder Theorem (CRT). Unlike the original "Ozaki I" (mantissa slicing), which scales quadratically with the number of slices, Ozaki II decomposes matrix multiplication into modular arithmetic over pairwise-coprime moduli.

Phase 1: Scale matrices to integers.
Phase 2: Perform low-precision (fp8) GEMMs modulo $m_i$ .
Phase 3: Reconstruct the integer product using Garner's algorithm and rescale to fp64.

The paper specifically adapts this for fp8 tensor cores (E4M3), utilizing a quantization trick to emulate modular arithmetic on floating-point units, as native int8 throughput has been deprioritized on B300/Rubin.

Implementation Strategy for Memory-Bound Kernels

A core contribution is the identification of register-level fusion as the mechanism to drive $\beta \to 1$ . The proposed implementation strategy involves:

Loading fp64 operands into shared memory.
Decomposing operands into residue planes within registers.
Executing $r$ low-precision tensor-core MMAs on these residue planes.
Reconstructing the result via Garner's algorithm in registers before writing back to global memory.
This ensures residue planes never touch HBM, preserving memory bandwidth.

3. Key Contributions

Unified Performance Model: The derivation of the TME model, which predicts the crossover arithmetic intensity where emulation outperforms native fp64, explicitly accounting for the $\alpha, \beta, \gamma$ parameters.
Kernel Design Discipline: The identification of register-level fusion as a correctness requirement for memory-bound kernels. Without this, the bandwidth inflation ( $\beta > 1$ ) negates the benefits of emulation.
Generational Projections: Performance projections for B300 and Rubin R200 showing that Ozaki II + fp8 can achieve:
- Memory-Bound Regime: Throughput matching the memory roof (e.g., 4 TFLOPS for stencils on B300), effectively restoring performance to pre-collapse levels.
- Compute-Bound Regime: Throughput ceilings of ~500 TFLOPS (B300) and ~400 TFLOPS (Rubin), exceeding the native fp64 ceiling of the previous generation (B200, 40 TFLOPS) by an order of magnitude.
H100 Baseline Comparison: A re-baselining against the H100 (the last HPC-balanced GPU). The paper demonstrates that Ozaki II on B300/Rubin matches or exceeds H100 performance across all workloads, whereas native B300 fp64 regresses by up to 50× on compute-sensitive tasks.
End-to-End Kernel Coverage: A comprehensive audit combining this paper's results with a companion FFT analysis [19] and BLAS-1 reduction strategies (FP32 + Kahan). The audit concludes that every major HPC kernel class (GEMM, SpMV, Stencils, FFT, reductions) admits a path to the memory roof at full fp64 accuracy on B300.

4. Results

Speedup Factors: On B300, Ozaki II/fp8 provides:
- ~380× speedup for Dense GEMM (compute-bound).
- ~24× speedup for Batched GEMV (B=8).
- ~3.1× speedup for 7-point Stencils.
- ~1.2× speedup for SpMV (deeply memory-bound).
Rubin Advantage: On the Rubin R200, the jump in HBM bandwidth (to 22 TB/s) combined with Ozaki II yields a 2.75× improvement over B300 in the memory-bound regime and a 6.6× improvement over H100 across the spectrum.
Substrate Choice: The paper confirms that fp8 is the superior substrate for Ozaki II on B300/Rubin due to the collapse of int8 throughput, offering a 30× emulation ceiling advantage over int8 on B300.
Accuracy: The emulation maintains provable componentwise error bounds comparable to native fp64, provided the moduli count $r$ is chosen correctly (typically $r \approx 10$ for fp8).

5. Significance and Claims

The paper argues that the "holy grail" of native fp64 silicon is no longer a prerequisite for credible scientific computing. Instead, the combination of abundant fp8 tensor throughput and Ozaki Scheme II emulation is sufficient to recover memory-roof execution at full fp64 accuracy across the entire canonical HPC kernel spectrum.

Key Claims:

Parity in Memory-Bound Regimes: Emulation does not penalize memory-bound kernels; with register-level fusion, it achieves parity with the memory roof, just as a healthy native fp64 chip would.
Superiority in Compute-Bound Regimes: Emulation vastly outperforms the native fp64 capabilities of the previous generation (B200) and the current generation's native fp64 units.
Strategic Viability: The engineering investment required to implement these kernels is now tractable on a timescale of "months rather than years," facilitated by modern AI coding assistants and the standardization of the algorithmic pattern.
Architectural Implication: Future GPU designs should ensure sufficient fp8 tensor throughput and a fallback path (such as the Kulisch INT32 sub-floor for spectral work) rather than insisting on native fp64 tensor cores. The paper posits that "fp8 (with the right algorithmic scaffolding) is all you need for production HPC."

The paper concludes that the "post-fp64 era" is not a regression but a strategic realignment where software-defined emulation converts the silicon savings from AI optimization into usable, high-precision scientific throughput.