An RRAM-based Hardware Implementation of a Radial Basis Function Neuron for Edge Classifiers

Technical Summary: RRAM-based Hardware Implementation of a Radial Basis Function Neuron for Edge Classifiers

Problem Statement
The deployment of modern Machine Learning (ML) models on resource-constrained edge devices faces significant challenges, particularly regarding energy efficiency, latency, and the ability to handle outliers or Out-of-Distribution (OOD) inputs in real-time. Traditional Deep Neural Networks (DNNs) often struggle with "domain shift"—where environmental changes, sensor noise, or evolving data patterns degrade the performance of pre-trained models. Furthermore, the von Neumann memory wall creates bottlenecks for computationally expensive operations like dot-products required for similarity searches. Existing solutions often lack the capability for efficient, on-device adaptation (continual learning) without requiring additional resources or data annotation, which is critical for safety-critical applications like autonomous navigation.

Methodology
The authors propose a hardware-native solution leveraging Metal-Oxide Resistive RAM (RRAM) integrated with CMOS technology to create an Analogue Content Addressable Memory (ACAM) system. The core of this design is a custom Template piXeL (TXL) cell, which functions as a configurable, analogue Radial Basis Function (RBF) neuron.

• TXL Cell Architecture: The TXL cell utilizes two source-degeneration RRAM-CMOS inverters. By programming the resistance of RRAM devices ($R_M$ and $R_B$) in series with the MOSFET sources, the circuit establishes a specific "matching window" defined by upper and lower voltage thresholds ($V_{TH}^{upper}$ and $V_{TH}^{lower}$). This window emulates a receptive field where the cell activates only when the input voltage falls within a specific range, effectively calculating a distance metric.
• Array Organization: TXL cells are organized into dense $k \times n$ arrays. Each row represents a unique $k$-dimensional prototype (stored as statistical attributes: mean $\mu$ and variance $\sigma$ encoded into RRAM conductance), and each column corresponds to an input feature.
• In-Memory Computing (IMC): The system performs similarity searches in parallel. Input vectors are applied as analogue signals to the bitlines. Through Kirchhoff's Current Law, the currents from individual TXL cells accumulate on the matchline, naturally computing the aggregate similarity score (inverse distance) between the input query and the stored prototype.
• Adaptation Policy: The system implements a three-tier adaptation policy based on the distance ($d$) between the input and the best-matching prototype:
  1. Reliable In-Distribution ($d \le \tau_{IDO}$): No adaptation occurs.
  2. In-Distribution Outlier ($\tau_{IDO} < d \le \tau_{OOD}$): The existing prototype is adapted (updated mean and variance) to include the new sample, mitigating gradual domain drift.
  3. Out-of-Distribution ($d > \tau_{OOD}$): The system identifies a novel class. A new prototype is allocated in an empty row of the array using a few-shot learning scheme, expanding the classifier's capabilities without overwriting existing knowledge.

Key Contributions

• Hardware-Native RBF Neuron: The paper introduces the TXL cell as a physical implementation of an RBF neuron, capable of performing metric-based classification directly in the analogue domain.
• Energy-Efficient Similarity Search: By utilizing RRAM-based ACAM, the design achieves $O(1)$ complexity for template matching, bypassing the memory wall.
• Online Adaptation Mechanism: The system supports "on-the-fly" learning where receptive field parameters can be tuned to track domain shifts or new classes without full model retraining.
• Explainability: Unlike opaque feed-forward layers, the decision-making process is explicitly traceable to the proximity of the input to stored prototypes, offering inherent explainability.

Results

• Energy and Latency: Circuit-level simulations (SPICE-Spectre) on a 180 nm CMOS process with TiN/HfON/TiN RRAM indicate an energy consumption of 185 fJ per cell per operation at 100 MHz. The latency per search is approximately 100 ns.
• Classification Accuracy:
  • On an artificial geometric symbol dataset, the system achieved 100% accuracy for both initial training and after adaptation.
  • On the MNIST dataset (downsampled to 7x7), the system achieved 89.1% accuracy pre-adaptation and 85.5% post-adaptation. The authors note the slight accuracy drop is attributed to the lack of feature extraction layers and the downsampling of the input, rather than the core TXL mechanism.
• Adaptation Performance: SPICE simulations demonstrated the system's ability to successfully adapt existing prototypes to outlier samples (reshaping the receptive field) and allocate new prototypes for unknown classes (e.g., introducing a "rectangle" class to a dataset of circles, triangles, and crosses) while maintaining the integrity of existing prototypes.

Significance
The paper claims that the proposed TXL-based architecture provides a viable path toward robust, energy-efficient edge computing for safety-critical applications. By enabling in-situ adaptation, the system addresses the challenge of domain shift, allowing edge devices to maintain reliability when encountering real-world data distributions that differ from training data. The authors position this technology as a step toward continual learning at the edge, where systems can expand their classification capabilities and adjust to new environments without catastrophic forgetting or the need for external data annotation. The work envisions future deployment in remote monitoring, wearable sensors, and autonomous navigation, provided that challenges regarding RRAM variability, retention, and endurance are managed through calibration.