💻 computer science

Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM

This paper explores the security implications of Processing-in-DRAM (PiD), highlighting its potential to enable efficient in-memory security primitives like high-throughput random number generators while simultaneously introducing new vulnerabilities such as amplified read disturbances and high-speed timing channels.

Original authors: Ismail Emir Yuksel, F. Nisa Bostanci, Ataberk Olgun, Onur Mutlu

Published 2026-06-23

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Ismail Emir Yuksel, F. Nisa Bostanci, Ataberk Olgun, Onur Mutlu

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine your computer is a busy restaurant. For decades, the kitchen (the processor) has been the star of the show. The waiters (the memory bus) have to run back and forth constantly, grabbing ingredients (data) from the pantry (the DRAM memory) and rushing them to the kitchen to be cooked. This running back and forth is slow, tiring, and wastes a lot of energy.

Memory-Centric Computing is a radical new idea: instead of the chef running to the pantry, we put a mini-stove right inside the pantry. Now, the ingredients can be chopped, mixed, and cooked right where they are stored. This is called Processing-in-DRAM (PiD).

This paper, written by researchers from ETH Zürich, explores what happens to security when we turn the "dumb" pantry into an "active" kitchen. It turns out, this new setup is a double-edged sword: it offers some amazing new security tools, but it also opens up some dangerous new ways for thieves to sneak in.

Here is a breakdown of their findings using simple analogies:

1. The Good News: New Security Superpowers

The researchers found that because the memory is now "alive" and doing work, it can generate two very important security tools that were previously hard to get:

The Unclonable Fingerprint (PUF):
Imagine every single DRAM chip is like a snowflake. Even though they are made in the same factory, tiny, random imperfections in their manufacturing make each one unique. The researchers showed that by "shaking" the memory (using specific electrical tricks), they can read these unique imperfections to create a digital fingerprint.
- Why it matters: This fingerprint is impossible to copy. It's like a lock that only opens with your specific snowflake. They built a system called SiMRA-PUF that creates these fingerprints faster and more reliably than previous methods, even on standard, off-the-shelf memory chips.
The True Random Number Generator (TRNG):
Computers need random numbers for encryption (like creating secret keys). Usually, computers just guess numbers based on a formula, which isn't truly random. The researchers found a way to use the memory itself to generate true randomness.
- How it works: They activate many rows of memory at once. The electrical signals from these rows clash and interfere with each other in a chaotic, unpredictable way (like a crowd of people shouting at once). This chaos is harvested to create a stream of numbers that is genuinely random.
- The result: Their system, SiMRA-TRNG, is incredibly fast (up to 16 billion bits per second) and works on regular memory chips without needing special hardware.

2. The Bad News: New Ways to Break In

Just as the new kitchen makes cooking faster, it also creates new ways for burglars to cause trouble or steal secrets.

The "Hammer" Effect (Read Disturbance):
In the old days, if you knocked on a door too hard, the neighbor might get annoyed. In this new system, the researchers found that if you "knock" (activate) multiple rows of memory at the same time, you can accidentally break the data in the rows right next to them.
- The discovery: They found that using the new "multi-row" cooking technique makes memory chips 158 times more vulnerable to this accidental breaking than before. It's like a gentle tap that used to do nothing now shatters the glass next to it. This is a major reliability risk that needs new defenses.
The Secret Whispering Channel (Timing Attacks):
In a normal computer, if you want to send a secret message, you have to go through a long, noisy hallway (the cache) to get to the main memory. The new PiD system lets applications go straight to the memory, skipping the hallway.
- The risk: Because the path is so direct and fast, two different programs running at the same time can "listen" to each other. One program can send a secret message by slightly delaying or speeding up its access to the memory. The other program measures exactly how long it takes to get a response and decodes the message.
- The result: The researchers built a tool called IMPACT that uses this trick to send secret messages at high speeds (14.8 Mb/s) or steal private data (like a user's DNA sequence) just by watching how long it takes for the memory to respond.

The Big Picture

The paper concludes that we need to stop thinking of computer memory as a passive storage box and start treating it as a combined workspace, storage room, and security vault.

While this new way of computing promises to be much faster and more energy-efficient, the researchers warn that we can't just flip a switch. We need to design these systems carefully to handle the new "noise" (the hammer effect) and block the new "whispering" (timing attacks). If we can solve these puzzles, we could build computers that are not only faster but fundamentally more secure.

Technical Summary: Memory-Centric Computing: Security Benefits and Challenges of Processing-in-DRAM

1. Problem Statement

Modern computing systems are predominantly processor-centric, treating main memory (DRAM) as a passive storage substrate. This architecture necessitates frequent data movement between processing elements (CPUs, GPUs, etc.) and memory, creating significant bottlenecks in performance, energy efficiency, and bandwidth. As data-centric applications like generative AI and large-scale machine learning grow, these bottlenecks become more critical.

While the Memory-Centric Computing (MCC) paradigm, specifically Processing-in-DRAM (PiD), offers a solution by moving computation to the data, its security implications remain underexplored. Shifting DRAM from an inactive store to an active computing substrate introduces a dual nature: it can provide new security primitives and reduce data exposure, but it simultaneously creates novel attack surfaces and exacerbates existing reliability issues. This paper investigates these security benefits and challenges, focusing on unmodified, commercial off-the-shelf (COTS) DRAM chips.

2. Methodology

The authors employ a rigorous experimental characterization approach using FPGA-based infrastructure (built upon SoftMC and DRAM Bender) to test real DRAM hardware. The methodology involves:

Hardware Testing: Extensive testing of hundreds of COTS DDR4 and LPDDR4 chips from major manufacturers.
Timing Violation Exploitation: Deliberately violating manufacturer-recommended DRAM access timing parameters (e.g., reducing activation latencies) to induce non-deterministic behaviors in DRAM cells.
Simultaneous Row Activation: Utilizing multiple-row activation (SiMRA) and consecutive multiple-row activation (CoMRA) techniques to trigger charge sharing and analog effects within the DRAM array.
Attack Simulation: Implementing specific attack vectors (e.g., RowHammer variations, timing channels) to measure their impact on system robustness and confidentiality.
Statistical Analysis: Evaluating entropy, uniqueness, stability, and throughput metrics for security primitives, and measuring bitflip rates and communication throughput for security challenges.

3. Key Contributions

A. Security Benefits: In-DRAM Security Primitives

The paper demonstrates that DRAM can serve as a high-performance substrate for two critical security primitives without requiring hardware modifications:

SiMRA-TRNG (True Random Number Generator):
- Mechanism: Exploits the charge-sharing process during simultaneous activation of multiple rows (up to 32) holding opposing data patterns. By reducing activation timings, the bitline voltage is perturbed randomly around the reference voltage ( $V_{DD}/2$ ), and the sense amplifier samples a random value.
- Performance: Achieves a throughput of up to 16.05 Gb/s, significantly outperforming prior state-of-the-art DRAM-based TRNGs (e.g., QUAC-TRNG).
- Quality: Generated bitstreams pass all NIST STS tests. Entropy increases with the number of simultaneously activated rows, though latency trade-offs exist.
SiMRA-PUF (Physical Unclonable Function):
- Mechanism: Similar to the TRNG, it uses simultaneous multiple-row activation with reduced timings to generate device-specific signatures based on manufacturing variations. Stable bits form the signature, while random bits are filtered out.
- Performance: Provides high repeatability (intra-Jaccard index >94%) and uniqueness (inter-Jaccard index <4%).
- Advantage: The 2-row activation variant achieves a 5.75% lower evaluation latency compared to the prior state-of-the-art (Frac-based PUF), making it suitable for runtime-accessible authentication.

B. Security Challenges: New Attack Surfaces

The paper identifies two critical risks introduced by PiD operations:

Amplified Read Disturbance (PuDHammer):
- Finding: PiD operations, which rely on activating multiple rows simultaneously or in quick succession, drastically exacerbate DRAM read disturbance vulnerabilities.
- Impact: The minimum number of activations required to induce the first bitflip ( $HC_{first}$ ) is reduced by up to 158.58x when using Simultaneous Multiple-Row Activation (SiMRA) compared to traditional RowHammer. Consecutive Multiple-Row Activation (CoMRA) also reduces $HC_{first}$ by up to 13.98x.
- Mitigation Cost: Adapting existing defenses like Per-Row Activation Counting (PRAC) to cover PiD operations incurs a significant system performance overhead (average 48.26%), indicating a need for new solutions.
High-Throughput Timing Channels (IMPACT):
- Finding: PiD allows user-space applications to bypass the cache hierarchy and access main memory directly. This enables high-throughput covert and side channels via the shared DRAM row buffer.
- Mechanism: Attackers exploit row-buffer conflicts (which take longer than hits) to encode data.
- Impact: The IMPACT-PuM covert channel achieves a communication throughput of 14.8 Mb/s, which is 6.5x higher than state-of-the-art main memory-based covert channels. A side-channel attack on genomic read mapping leaked private query characteristics with 96% accuracy at 7.6 Mb/s.
- Mitigation: Existing defense mechanisms to eliminate these timing channels incur high performance overheads, suggesting that low-overhead solutions are still an open research problem.

4. Results

TRNG: SiMRA-TRNG generates high-quality random numbers across various DRAM densities and die revisions, with throughput scaling up to 16.05 Gb/s.
PUF: SiMRA-PUF generates unique, repeatable signatures with lower latency than previous methods, validating its use for runtime authentication.
Vulnerability: PiD operations make DRAM chips significantly more susceptible to data corruption (bitflips) than standard access patterns, with the "double-sided" SiMRA attack being the most potent.
Leakage: Direct memory access in PiD systems enables timing attacks with throughput orders of magnitude higher than traditional cache-based attacks, posing a severe threat to data confidentiality.

5. Significance and Outlook

The paper argues that the future of computing lies in treating memory not as an inactive substrate, but as a combined computation, storage, and security substrate.

Paradigm Shift: The authors assert that it is time to design and program DRAM with security as a key goal alongside computational capability and storage density.
Dual Nature: While PiD offers a path to fundamentally more secure systems by eliminating data movement over the main memory bus (a major attack vector) and enabling in-memory security primitives, it simultaneously amplifies robustness and confidentiality risks.
Call to Action: The paper concludes that while the potential of memory-centric systems is bright, widespread adoption requires solving significant challenges across the computing stack. Specifically, the mindset and infrastructure shift required to manage these new security trade-offs represents the largest hurdle to overcome. The authors emphasize that enabling secure, energy-efficient, and high-performance PiD systems is a critical, yet unresolved, research direction.