Weave: Verified Netlist-to-Schematic Conversion via Layered Graph Layout

Technical Summary: Weave – Verified Netlist-to-Schematic Conversion via Layered Graph Layout

Problem Statement
In Electronic Design Automation (EDA), the SPICE netlist serves as the standard language for circuit simulation, yet it is not the primary medium for human engineering reasoning. Designers rely on schematics to understand structure, trace signal flow, and debug behavior. As machine learning methods increasingly generate circuits directly as netlists, a bottleneck emerges: converting these machine-produced netlists back into readable, accurate diagrams. Existing learning-based approaches (e.g., Schemato) translate netlists into schematics probabilistically. However, these methods suffer from two critical limitations: their accuracy degrades sharply as circuit complexity increases (specifically beyond five components), and they offer no guarantee of correctness, relying instead on continuous similarity scores (like Graph Edit Distance) rather than binary verification of connectivity.

Methodology
Weave addresses these issues through a deterministic, verification-first pipeline that converts SPICE netlists into LTspice .asc schematic files. The process consists of the following stages:

1. Parsing and Net Classification: The system parses standard SPICE elements (passives, active devices, subcircuits, etc.). Nets are classified as ground, supply rails, or signals. Ground and rail nets are treated as flags (local connections) rather than drawn wires to maintain legibility, while only signal nets enter the layout graph.
2. Layered Layout: Signal components are mapped to nodes in a graph processed by elkjs, an implementation of the Sugiyama framework. This engine performs a left-to-right layered layout with orthogonal routing. Node sizes account for symbol bodies and pin escapes, snapping to LTspice's 16-unit grid.
3. Placement Patterns: Specific structures that degrade the main signal chain (e.g., local/far feedback loops, divider legs, shunts, supply corners) are handled via explicit placement patterns rather than the general graph. These patterns place elements relative to existing nodes and emit direct, net-tagged connections.
4. Symbol Handling: Weave embeds a pin table for 5,093 LTspice symbols. If a netlist references a part with a pin count mismatch or an unknown part, the system substitutes a synthetic rectangular block sized to the pin count. While the glyph is generic, the connectivity and name remain exact, ensuring the schematic compiles and passes verification.
5. Round-Trip Verification: This is the core of the system's correctness claim. Every generated .asc file is re-parsed into a netlist. The connectivity partitions of this regenerated netlist are compared, net-for-net, against the original input. A result is reported as correct only if the partitions are identical.
6. Safe-Mode Ladder: If the default layout fails verification, Weave iteratively retries with progressively simpler modes (disabling placement patterns, falling back to pure elkjs layout, or widening channel spacing). It retains the first result that passes the verifier, ensuring that any reported output is connectivity-perfect, even if visually less compact.

Key Contributions
The paper presents three primary contributions:

1. A Deterministic, Verification-First Pipeline: Unlike learning-based methods, Weave revives the classical layered-flow layout approach using a modern industrial graph engine (elkjs) combined with specific placement patterns. It requires no training, no GPU, and no probabilistic sampling.
2. Round-Trip Connectivity Verification: The system provides a binary correctness certificate. Instead of a similarity score, it guarantees that the generated schematic preserves the original connectivity exactly (equivalent to a Graph Edit Distance of 1.0). To the authors' knowledge, no prior netlist-to-schematic method certifies connectivity in this manner.
3. A Safe-Mode Ladder: This mechanism ensures that the system never produces a "wrong" schematic. If a complex layout fails verification, the system degrades gracefully to simpler layouts until a verified match is found.

Results
The authors evaluated Weave on two datasets:

• Circuits-LTSpice Benchmark: On the identical 117-circuit test set used by the state-of-the-art LLM converter Schemato, Weave achieved 100% compilation and 100% round-trip-verified connectivity equivalence. In contrast, Schemato reported 76% compilation and a Graph Edit Distance similarity of 0.35. Notably, 73% of the circuits in this set exceeded the five-component threshold where Schemato reportedly loses connectivity accuracy.
• Large Corpus (Analog Devices LTspice Demo Collection): On a larger, denser corpus of 3,460 netlistable circuits (mean 14.4 elements, max 138), Weave verified exact connectivity for 88.4% of circuits. The remaining failures were concentrated in a specific class of dense multi-pin power modules, and conversion errors were primarily due to symbols absent from the installed library (parts newer than the LTspice version used).

Significance and Claims
The paper argues that for a converter to be useful in an engineering workflow, connectivity correctness must be guaranteed by construction and verified, rather than approximated and scored. The authors position Weave not as a competitor in aesthetic optimization (which learning-based methods emphasize), but as a "stronger primitive" that ensures the schematic is right before it is made pretty.

The significance lies in shifting the paradigm from probabilistic generation with similarity metrics to deterministic construction with binary verification. The authors claim that while learning-based models struggle with scale and data scarcity, Weave sidesteps these issues through a deterministic symbol table and a generic-block fallback. The paper concludes that "correctness by construction with verification" is both achievable and decisively stronger than learned approximation for netlist-to-schematic conversion, providing a reliable tool for integrating domain experts into automated design loops. Future work is identified as addressing dense multi-pin modules and deep cascade topologies through box-contract layouts and hierarchical generation.