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Low-latency FPGA-based electronic control system for fast preparation of defect-free atom arrays

This paper presents a low-latency, FPGA-based electronic control system that integrates photon counting and real-time decision-making to achieve a 282 µs feedback loop, successfully demonstrating the high-fidelity assembly of defect-free neutral atom arrays through iterative rearrangement.

Original authors: Ya-Dong Hu, Dong-Qi Ma, Tian-Yang Zhang, Liang Chen, Yi-Chen Zhang, Xiao-Kang Zhong, Wen-Yi Zhu, Hong-Jie Fan, Qing-Xuan Jie, Yan-Lei Zhang, Gang Li, Xi-Feng Ren, Xu-Liang Zhang, Guang-Can Guo, Zhu-Bo

Published 2026-07-10

📖 4 min read☕ Coffee break read

CC BY 4.0

Original authors: Ya-Dong Hu, Dong-Qi Ma, Tian-Yang Zhang, Liang Chen, Yi-Chen Zhang, Xiao-Kang Zhong, Wen-Yi Zhu, Hong-Jie Fan, Qing-Xuan Jie, Yan-Lei Zhang, Gang Li, Xi-Feng Ren, Xu-Liang Zhang, Guang-Can Guo, Zhu-Bo Wang, Chang-Ling Zou

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you're trying to build the perfect team of 10 robots for a heist, but you can only grab them from a chaotic crowd of 24. In the world of quantum computing, these "robots" are atoms, and the "crowd" is a grid of invisible laser traps called optical tweezers. The problem? When you turn on the lasers, the atoms don't always land where you want them. Some traps are empty, some have two atoms, and most have just one. To get a perfect team of 10, you have to shuffle the lucky ones around.

For a long time, this shuffling was like asking a slow, overworked librarian (a standard computer) to check every book, decide who needs to move, and then tell the movers where to go. By the time the librarian finished, the atoms had already cooled down or moved on, making the whole process too slow for the high-speed game of quantum computing.

The Big Breakthrough: Cutting Out the Middleman
In this new study, the researchers built a super-fast electronic control system that kicks the "librarian" (the personal computer) out of the loop entirely. Instead of sending data to a PC to think about it, they put the brain directly into the hardware using a chip called an FPGA. Think of it as replacing the slow librarian with a lightning-fast reflex system that sees the problem and moves the atoms before you can even blink.

How Fast is "Fast"?
The paper measured this speed with extreme precision. The entire process—from seeing where the atoms are, deciding where they need to go, and actually moving them—takes only 282(19) µs (microseconds). To put that in perspective, old systems using a PC took over 7 ms (milliseconds). That's a massive difference; it's the difference between a snail crossing a room and a hummingbird doing it in a flash.

The "Volcano" Setup
To make this speed possible, they used a clever trick called "optical channel mapping," which the authors describe as a "volcano architecture." Imagine a volcano where every atom sits in its own crater, and a unique tube (a waveguide) carries the light from that specific atom directly to its own detector. This means the system can check all 24 traps at the exact same time, rather than checking them one by one.

The Results: From Chaos to Perfection
Here is what happened when they tested this new system:

The First Try: When they tried to assemble a perfect team of 10 atoms from the 24 available traps in a single shuffle, they succeeded about 65.7% of the time.
The Power of Iteration: But the system is so fast that it can do this over and over again in the time it takes to blink. By running the shuffle five times in a row, using the extra atoms as a backup pool, they boosted their success rate to 95.4%.
Filling the Gaps: In a single round of rearrangement, they managed to fill 96% of the target spots with exactly one atom, a huge improvement over the messy initial state.

Why This Matters (And What It's Not)
The paper is very clear about what this system doesn't do yet. It doesn't solve the problem of atoms getting too hot or moving too roughly; in fact, the researchers had to add a specific cooling step (called GMC) for 2 ms to keep the atoms calm enough to move without flying away. The system also doesn't magically create atoms out of thin air; it just rearranges the ones it already has.

However, the authors are confident that this low-latency system is the missing piece of the puzzle for the future. They suggest that by removing the PC bottleneck, this setup paves the way for "mid-circuit measurement" (checking on the atoms while the quantum computer is still working) and real-time error correction. It's not a finished quantum computer yet, but it's the high-speed nervous system that one will need to make a giant, fault-tolerant quantum brain work.

In short, the researchers proved that by building a custom, PC-free brain for their atom-shuffling robot, they can rearrange atoms with a speed and success rate that was previously impossible, bringing us one step closer to building a quantum computer that actually works.

Technical Summary: Low-latency FPGA-based Electronic Control System for Fast Preparation of Defect-free Atom Arrays

Problem Statement
Neutral atom arrays have emerged as a leading platform for universal quantum computation and many-body physics, demonstrating gate fidelities that surpass the thresholds required for quantum error correction (QEC). However, realizing fault-tolerant quantum processors is currently hindered by the lack of dedicated, scalable, low-latency electronic control systems capable of real-time feedback. Existing demonstrations of QEC rely on post-processing data because conventional control architectures, which depend on a personal computer (PC) for feedback loops, introduce latencies (typically >7 ms) that exceed the execution times of quantum circuits (hundreds of microseconds). This bottleneck prevents critical capabilities such as defect-free atom array assembly, real-time compensation for atom loss, mid-circuit measurement, and real-time QEC.

Methodology
The authors present a unified, PC-free electronic control system built on a PXIe architecture (PXIe-QC100) that integrates photon counting, real-time decision-making, and waveform generation entirely within FPGA hardware. The system employs a "volcano architecture" utilizing optical channel mapping (OCM) to route fluorescence from individual atoms to single-photon detectors (SPDs) for parallel readout.

The control loop operates as follows:

Detection: Fluorescence counts are accumulated by a counter card and binarized (occupied vs. vacant) by an embedded ARM processor on the card, comparing counts against a preset threshold.
Decision: The ARM processor calculates atom rearrangement paths based on the binary occupancy map.
Actuation: Radio-frequency (RF) movement commands are transmitted via a high-speed backplane to an Arbitrary Waveform Generator (AWG) card, which drives an Acousto-Optic Deflector (AOD) to move atoms.
Optimization: To minimize latency, the system transmits binarized comparison results rather than raw photon counts and uses compact instruction sets rather than streaming full time-domain waveforms.

The system was validated using a 1D array of 24 optical dipole traps (852 nm) to assemble defect-free target arrays. The experimental sequence includes a 150 ms magneto-optical trap (MOT) loading stage, followed by cooling (PGC and Grey Molasses Cooling) and fluorescence detection. To mitigate atom loss during transport, a 2 ms Grey Molasses Cooling (GMC) pulse is applied, reducing atomic temperature to ~30.6 µK.

Key Contributions

PC-Free Architecture: The system eliminates the PC from the feedback loop, relegating it solely to a configuration role. All data acquisition, processing, and feedback logic are executed on FPGA and embedded ARM hardware.
Ultra-Low Latency: The system achieves a total feedback latency of 282(19) µs, a significant reduction compared to PC-based systems (>7 ms).
Modular Scalability: The PXIe chassis supports up to 8 slots for counter and AWG cards, with potential for expansion to 18 slots and synchronization across multiple chassis.
Iterative Rearrangement Protocol: The low latency enables multi-round feedback iterations within a single MOT loading cycle, allowing surplus atoms to be used to fill defects in subsequent rounds.

Results

Single-Round Performance: Rearranging atoms from 24 stochastically loaded traps into a target zone of 10 atoms achieved a filling fraction of ~96%. The success probability for generating a defect-free 10-atom array in a single round was 65.68%, compared to a negligible probability for stochastic loading alone.
Multi-Round Performance: By utilizing the low-latency system for iterative feedback over five rounds, the success probability for generating a defect-free 10-atom array increased from 65.68% to 95.38%. For target sizes of 8 and 12 atoms, the success probabilities reached 99.01% and 88.78%, respectively, after five rounds.
Latency Breakdown: The total latency of ~282 µs is composed of:
- Readout latency ( $t_{read}$ ): ~7.51 µs (for 24 traps).
- Calculation latency ( $t_{calculate}$ ): ~0.89 µs.
- Transmission latency ( $t_{PS \to PL}$ ): ~261.58 µs (dominated by the current placement of the ARM processor).
- Transmission latency ( $t_{PL \to PL}$ ): ~4.80 µs.

Significance and Claims
The paper claims that this system establishes the necessary electronic infrastructure for mid-circuit measurement and real-time quantum error correction on neutral-atom platforms. By reducing feedback latency to the sub-millisecond scale, the system enables the practical execution of algorithms requiring real-time decision-making, such as active error correction and dynamic circuit execution.

The authors note that the current single-round limit is dictated by atomic physics (temperature and transport trajectory) rather than electronic control. They project that future architectural optimizations—specifically moving the ARM processor into a higher-performance AWG-card FPGA—could reduce total latency to below 35 µs for 64 atoms and ~400 µs for 1000 atoms. The system is presented as a robust hardware foundation for scaling neutral atom quantum processors toward fault tolerance.

Technical Summary: Low-latency FPGA-based Electronic Control System for Fast Preparation of Defect-free Atom Arrays

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