Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis

Technical Summary: Vogls – A Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis

Problem Statement
Designing hardware resistant to side-channel attacks (SCA) increasingly relies on pre-silicon simulation to predict device leakage before fabrication. However, current functional verification simulators are ill-suited for SCA workflows. SCA requires generating large numbers of short trace collections with slight input variants, a task for which standard simulators are inefficient. Existing academic tools often follow a three-step pattern: capturing signal traces (often in VCD/SAIF/FST formats), converting them to synthetic power traces using models like Hamming Weight, and performing statistical analysis. This process is hindered by two main issues:

1. Performance: Simulating millions of traces for large designs takes prohibitive time, and the resulting trace files become excessively large, making storage and conversion costly.
2. Interactivity: Standard simulators lack fine-grained control over the simulation state. They typically require restarting from reset for every trace, failing to support "forking" (reusing setup logic) or interactive mutation of states required for adaptive attacks.

Furthermore, existing open-source simulators fail to simultaneously meet three critical criteria for SCA: efficiency (fast trace collection), interactivity (state manipulation), and versatility (support for full-timing, multi-abstraction levels, and 4-value logic). Commercial simulators are efficient and versatile but lack interactivity and source code availability.

Methodology and Design
The authors present Vogls (Versatile Open Gate Level Simulator), an open-source Verilog simulator written in Rust, designed specifically to bridge the gap between compiled-code performance and full-timing simulation interactivity.

• Architecture: Vogls follows a compiler-like structure. It tokenizes, parses, and elaborates Verilog (including SDF annotations) into a custom Vogls Intermediate Representation (VIR).
• Vogls Intermediate Representation (VIR): VIR is a temporally-aware, unified target inspired by LLHD but extended to support non-synthesizable Verilog concepts (e.g., delay controls, specify blocks). It uses Static Single-Assignment (SSA) and Control-Flow Graphs (CFGs) to model processes, signals, and timing. It supports both 2-value and 4-value logic.
• Execution Strategies: The optimized VIR can be executed via:
  1. A bytecode interpreter for fast iteration and short runs.
  2. Compiled C code (transpiled to native instructions) for high-performance, repeated runs.
• State Management: A core innovation is the separation of the design (constant, read-only) from the simulation state (time, signal values, listeners). This allows the simulator to fork the state. A workflow can run setup logic once, fork the state at a point-of-interest, and then simulate short windows with varied inputs without re-initializing the design. This preserves timing and leakage characteristics while eliminating redundant setup simulation.
• Interface: Vogls provides a Python interface allowing users to pause, inspect, mutate signals, and fork simulations without modifying the hardware design.

Key Contributions

1. First Combined Simulator: Vogls is the first open-source simulator to combine compiled-code performance, full-timing simulation, and fine-grained state control (forking/mutation).
2. VIR Implementation: It introduces a unified intermediate representation capable of handling semantics from cycle-accurate to full-timing simulations, including Verilog-specific timing constructs.
3. Efficient Trace Collection: By utilizing state forking, Vogls eliminates the need to re-simulate from reset for every trace, significantly reducing the time required to collect large datasets.
4. Pre-silicon SCA Workflow: The tool supports a complete workflow from RTL to full-timing Gate-Level (GTL) abstraction levels, implementing standard power models (Hamming Weight/Distance).

Experimental Results
The authors benchmarked Vogls against Verilator (efficient, cycle-accurate, 2-value) and Icarus Verilog (versatile, interpreted, 4-value) on three workloads:

1. PicoRV32 (RTL): Calculating the 1000th prime.
2. Masked Canright SBOX (RTL): Verifying masked logic.
3. UART + AES (Full-timing GTL): Timing-annotated gate-level simulation using an ICE40 FPGA netlist.

• Performance:
  • On the full-timing AES design, Vogls (compiled) simulated 5.9 times faster than Icarus Verilog (12.8s vs. 76.2s). Verilator could not run this experiment due to a lack of full-timing support.
  • On the PicoRV32 RTL design, Vogls (compiled) was only 30% slower than Verilator (1.8s vs. 1.4s) while offering full-timing capabilities and 4-value logic support.
• Case Study (DPA Attack):
  • The authors performed a Differential Power Analysis (DPA) attack on an AES implementation at RTL, GTL, and full-timing GTL levels.
  • Using the forking workflow, they captured 30,000 traces.
  • Results: The attack successfully recovered the key at all abstraction levels. The Minimum Traces to Disclosure (MTD) increased with model fidelity (6,897 for RTL, 13,154 for GTL, 18,341 for full-timing GTL), demonstrating that more accurate timing models reveal more subtle leakage but require more traces to exploit.

Significance and Claims
The paper claims that Vogls fills a critical gap in the open-source hardware design toolbox, which currently lacks a tool capable of fast, scriptable, full-timing simulation. By enabling efficient trace collection and interactive state manipulation, Vogls makes previously infeasible pre-silicon SCA workflows practical.

The authors emphasize that Vogls is not intended to replace mature tools like Verilator or Icarus Verilog for general functional verification. Instead, it is a purpose-built tool for the specific needs of SCA research. It offers a lightweight, extensible foundation (via VIR) that supports the necessary concepts for full-timing simulation and trace collection while remaining open-source. The paper concludes that by open-sourcing Vogls, the authors aim to motivate further exploration into purpose-built simulators for side-channel analysis.