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NeuroAbs: A Neuro-Symbolic RTL Abstraction Framework for Property Checking Acceleration

This paper presents NeuroAbs, a neuro-symbolic framework that leverages LLMs for RTL signal identification and AST-based symbolic representation, combined with SMT-based soundness checking and CEGAR refinement, to automate RTL abstraction and significantly accelerate hardware property checking.

Original authors: Zhiyuan Yan, Xiaofeng Zhou, Ziyue Zheng, Ziyi Yang, Wenbin Che, Wei Zhang, Yangdi Lyu, Hongce Zhang

Published 2026-08-19

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Zhiyuan Yan, Xiaofeng Zhou, Ziyue Zheng, Ziyi Yang, Wenbin Che, Wei Zhang, Yangdi Lyu, Hongce Zhang

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

In the hidden world of modern electronics, the chips that power our phones, cars, and computers are built from billions of tiny switches. Before these chips are ever manufactured, engineers must prove that they will behave exactly as intended, no matter what instructions they receive. This process, known as formal verification, is a rigorous mathematical check that ensures a design is free of hidden flaws. However, as these designs grow more complex, the task of checking them becomes overwhelming. The sheer number of possible states a chip can enter is so vast that even the most powerful computers struggle to explore them all in a reasonable time. To solve this, engineers often use a technique called abstraction, which simplifies a complex design by removing details that do not matter for a specific test, much like looking at a map of a city that shows only the main roads needed for a specific trip while ignoring every side street and alley.

For years, creating these simplified models required either tedious manual work by human experts or relied on rigid, pre-programmed rules that often missed the nuances of a specific design. A new approach called NeuroAbs offers a different path, combining the pattern-recognition strength of artificial intelligence with the strict logic of formal mathematics. This method uses large language models—advanced AI systems trained on vast amounts of text—to understand the intent behind a hardware design and a specific property it needs to satisfy. The AI identifies which parts of the circuit are irrelevant to the current test and suggests how to simplify them. However, because AI can sometimes make mistakes or suggest changes that break the logic, the system does not trust the AI blindly. Instead, it acts as a neuro-symbolic framework, where the AI proposes changes and a separate, rigorous mathematical engine immediately checks if those changes are safe. If the simplification is too aggressive and risks hiding a real error, the system automatically refines the model, peeling back the layers of simplification just enough to restore accuracy without losing the speed benefits.

The researchers behind NeuroAbs tested their framework on several real-world processor designs and peripheral components, including a common communication interface used in many devices. They found that the system could successfully identify opportunities to simplify the logic that traditional rule-based methods missed. For instance, when verifying a specific instruction in a processor, the AI realized that the logic handling other, unrelated instructions could be safely replaced with a generic placeholder. This allowed the verification engine to focus only on the relevant parts of the circuit. In experiments, this approach significantly accelerated the time required to prove that a design was correct. When the researchers integrated NeuroAbs with existing high-performance verification tools, the time needed to reach a formal proof dropped by nearly half in many cases. Even when a complete proof was not possible within the time limit, the simplified models allowed the system to explore much deeper into the circuit's behavior, uncovering potential bugs that would have otherwise remained hidden.

The success of this method relies on a careful balance between the flexibility of the AI and the precision of formal logic. The system first analyzes the design and the specific test scenario to pinpoint which signals are critical. It then uses the AI to rewrite the code in those specific areas, replacing complex calculations with simpler, abstract values. Crucially, every single rewrite is subjected to a strict mathematical check to ensure it does not alter the fundamental behavior of the chip in a way that would invalidate the test. If the check fails, the system uses a feedback loop to identify exactly which simplification caused the problem and reverts that specific part to its original form. This iterative process ensures that the final model is both simple enough to verify quickly and accurate enough to be trusted. The results show that this hybrid approach can handle diverse types of hardware logic, from simple arithmetic operations to complex branching structures, making it a powerful tool for the next generation of chip design.

By automating the creation of these simplified models, NeuroAbs addresses a major bottleneck in hardware engineering. Previously, the decision of what to simplify and how to do it depended heavily on human intuition or fixed rules that could not adapt to every unique design challenge. This new framework demonstrates that artificial intelligence can be effectively guided to perform these tasks, provided it is anchored by a system that verifies every step. The findings suggest that the future of hardware verification may lie in such collaborative systems, where machines handle the heavy lifting of pattern recognition and suggestion, while mathematical rigor ensures the safety and correctness of the final product. As chip designs continue to grow in complexity, tools like NeuroAbs offer a promising way to keep pace, ensuring that the devices we rely on are built on a foundation of verified truth.

Technical Summary: NeuroAbs

Problem Statement

Formal verification, specifically property checking (model checking), is essential for ensuring the functional correctness of hardware designs. However, as Register-Transfer-Level (RTL) designs grow in size and complexity, efficiently proving user-specified properties becomes a significant bottleneck. While abstraction techniques are commonly used to reduce system complexity by replacing concrete models with simplified representations, existing methods face two primary limitations:

Manual Abstraction: Relies heavily on human insight and is labor-intensive, requiring engineers to manually identify which parts of the design are irrelevant to a specific property.
Rule-Based Automatic Abstraction: Techniques such as structural abstraction, syntax-guided abstraction, and datapath abstraction (e.g., replacing arithmetic with uninterpreted functions) lack flexibility. They often fail to identify abstraction opportunities that depend on the specific semantic intent of a verification scenario and the target property, as they rely on predefined syntactic rules rather than functional understanding.

Consequently, current methods often miss opportunities to safely abstract logic that is irrelevant to a specific verification goal, or they produce abstractions that are either too coarse (leading to spurious counterexamples) or too conservative (failing to accelerate verification).

Methodology: The NeuroAbs Framework

The paper proposes NeuroAbs, a neuro-symbolic framework that integrates Large Language Models (LLMs) with symbolic reasoning to automate RTL abstraction. The framework operates in three distinct stages:

1. LLM-Assisted Signal Analysis (Neural Component)

Instead of feeding entire RTL codebases to an LLM, which exceeds context limits, NeuroAbs employs a Signal Analyzer to identify candidate signals for abstraction.

Input: Design specifications, verification scenario descriptions, and signal definitions.
Process: Using Chain-of-Thought (CoT) prompting and custom system instructions, the LLM analyzes the verification scenario to identify "scenario-related signals." It determines which signals control the logic relevant to the specific property and suggests fixed values (e.g., setting an opcode to a specific instruction type).
Static Analysis Integration: The LLM's output is combined with RTL static analysis (e.g., constant propagation) to localize the specific code regions and statements affected by these signals. This narrows the scope from the entire design to a small set of candidate statements.

2. AST-Guided Abstraction (Neuro-Symbolic Core)

To ensure structural integrity and prevent the LLM from rewriting unrelated logic, NeuroAbs converts the RTL into an Abstract Syntax Tree (AST).

Localization: The system maps the identified candidate signals to specific statement-level AST nodes and their enclosing structural contexts (e.g., always blocks, case statements).
Transformation: A second LLM, the Abstractor, is tasked with rewriting only the localized AST nodes. It uses few-shot learning (providing examples of original vs. abstracted statements) to generate candidate abstractions.
Constraint: The LLM is constrained to rewrite only the specific parts of a statement deemed irrelevant to the property (e.g., replacing an AND operation with an unknown value X if the property only concerns ADD operations), while preserving the relevant logic.

3. Symbolic Validation and Refinement (Symbolic Component)

Every generated abstraction is rigorously validated to ensure it is a sound over-approximation of the original design.

SMT Checking: The framework uses Satisfiability Modulo Theories (SMT) solvers (specifically Z3) to verify the condition $\forall V, S(V) \implies \hat{S}(V)$ $\forall V, S (V) ⟹ \hat{S} (V)$ . This ensures that every behavior allowed by the abstract statement is also allowed by the original.
- Handling X-values: Since SMT solvers do not natively support unknown values (X), these are translated into fresh variables bound by existential quantifiers ( $\exists Y$ ) to allow the solver to treat them as non-deterministic choices.
Customized CEGAR Loop (R-CEGAR): If the abstract model fails to prove the property and generates a counterexample, the system checks if the counterexample is spurious.
- If spurious, a counterexample reduction technique is applied to generalize the trace and pinpoint exactly which abstracted statement triggered the violation.
- The system then reverts only the specific invalid statements to their original form, rather than discarding the entire abstraction, and iterates the process.

Key Contributions

First Application of LLMs to RTL Abstraction: The paper introduces NeuroAbs as the first framework to utilize LLMs for identifying and generating RTL abstractions, moving beyond static rule-based approaches.
Neuro-Symbolic Workflow: It proposes a novel flow where the neural component (LLM) proposes scenario-aware candidates, while the symbolic component (AST traversal and SMT) constrains the rewriting to precise structural targets and validates soundness.
Customized Refinement (R-CEGAR): The authors introduce a refinement loop that uses counterexample reduction to efficiently identify and revert only the specific abstract statements causing spurious counterexamples, minimizing the number of iterations required.

Experimental Results

The framework was evaluated on a suite of benchmarks including RISC-V processor cores (PicoRV32, Piccolo, Flute) and an I2C peripheral, covering 55 verification scenarios. The results were compared against state-of-the-art model checkers (AVR and RIC3) which already include advanced abstraction mechanisms.

Formal Proof Acceleration: When integrated with AVR, NeuroAbs reduced the average runtime for constructing formal proofs by 44.89%. Even with AVR's existing abstraction capabilities, NeuroAbs provided significant additional speedups.
Bug-Finding Efficiency (BMC): For cases where formal proofs could not be completed within the time limit, NeuroAbs significantly accelerated the Bounded Model Checking (BMC) process.
- In the "Piccolo" case, the average unrolling depth increased from 109.36 to 125.36 cycles.
- In the "Flute" case, the time required to reach the baseline's maximum depth was reduced by 75.98%.
Ablation Studies: Experiments confirmed that both few-shot learning and custom instructions are critical. Removing few-shot learning dropped the over-approximation rate from 95.27% to 83.51%. Removing custom instructions led to a 98.38% drop in "strict" over-approximations (meaning the model tended to reproduce original statements rather than abstracting them).
Complexity Reduction: Analysis of the resulting And-Inverter-Gate (AIG) circuits showed a substantial reduction in the maximum variable index, confirming that NeuroAbs effectively simplifies circuit structure.

Significance and Claims

The paper claims that NeuroAbs addresses the rigidity of traditional rule-based abstraction and the labor intensity of manual methods. By combining the semantic reasoning capabilities of LLMs with the rigor of symbolic verification, NeuroAbs can identify context-specific abstraction opportunities that static rules miss.

The authors position NeuroAbs not as a replacement for existing model checkers, but as a complementary framework that enhances their efficiency. The results demonstrate that even when integrated with highly optimized, competition-winning model checkers (AVR and RIC3), the neuro-symbolic approach yields measurable improvements in both proof construction speed and bug-finding depth. The framework is presented as a step toward more automated, scenario-aware hardware verification that reduces the reliance on manual expert intervention.