🔬 materials science

Sidewall Metrology Protocol for Superconducting Qubit Devices

This paper establishes a standardized scanning probe microscopy-based protocol for quantitatively characterizing superconducting qubit sidewall morphology through new descriptors, enabling cross-laboratory comparisons and future investigations into the correlation between sidewall geometry and qubit performance.

Original authors: Jørgen Garnæs, Henrik S. Guttesen, Astrid T. Rømer, Oscar Danielsson, Emily P. Duggan, Zhenhai Sun, Asen Lyubenov Georgiev, Li Wei Chang, Morten Kjaergaard, Mark Bieler, Lukas Grünhaupt, Sabbir A. Kha

Published 2026-10-20

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CC BY 4.0

Original authors: Jørgen Garnæs, Henrik S. Guttesen, Astrid T. Rømer, Oscar Danielsson, Emily P. Duggan, Zhenhai Sun, Asen Lyubenov Georgiev, Li Wei Chang, Morten Kjaergaard, Mark Bieler, Lukas Grünhaupt, Sabbir A. Khan

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

In the quest to build machines that can solve problems beyond the reach of today's computers, scientists are turning to a technology that relies on the strange rules of quantum mechanics. At the heart of these machines are tiny circuits called superconducting qubits, which act as the basic units of information. To function correctly, these circuits must be incredibly stable, holding onto their quantum state without losing energy to their surroundings. However, even when built with the same design, these devices often behave differently from one another, with some lasting much longer than others. Researchers suspect that the secret to this inconsistency lies not just in the materials used, but in the microscopic shape of the circuit's edges. Just as a rough road can slow down a car, microscopic imperfections on the walls of these circuits can trap energy and cause the computer to fail. Understanding these hidden shapes is crucial, but they are so small and complex that standard tools struggle to measure them accurately.

A team of researchers from institutions in Denmark and Germany has developed a new way to map these invisible edges with high precision. They focused on the vertical walls of the metal structures that make up the qubits, which are typically made of aluminum. While previous methods could take a flat, two-dimensional picture of a cut slice of the device, the new approach uses a scanning probe microscope to trace the actual surface of the wall from top to bottom. This technique allows them to see the wall as it truly exists in three dimensions, capturing every tiny bump, dip, and curve that might interfere with the flow of electricity. By creating a detailed map of these surfaces, the team established a standardized protocol for measuring them, ensuring that scientists in different laboratories can compare their results using the same rules.

The researchers applied this new method to several key parts of the qubit devices, including the main capacitor pads and the tiny Josephson junctions that control the flow of current. They found that the walls are rarely perfectly smooth or straight. Instead, they exhibit a variety of shapes, from gentle slopes to sharp, jagged protrusions. To describe these shapes, the team introduced two new ways of measuring the surface. The first measures the roughness along the length of the wall, quantifying how much the edge wavers side-to-side. The second measures the sharpness of the curves on the wall itself. They discovered that some walls have tiny, sharp points that are only about 10 nanometers in radius, a scale so small that it is comparable to the size of a single virus. These sharp points are significant because they can concentrate electric fields, potentially creating weak spots where energy is lost.

The study revealed that the shape of these walls varies significantly, even between different parts of the same chip. Some devices had walls that were relatively smooth, while others showed deep pits or sharp spikes. The researchers noted that a single measurement is not enough to describe a whole device; one edge might look perfect while another nearby is quite rough. This variability suggests that the manufacturing process leaves behind subtle differences that can impact how long the qubit survives before losing its information. The team also found that the tools used to measure the walls, specifically the tiny tip of the microscope, can influence the results. If the tip is too blunt, it might miss the smallest details, much like a large brush cannot paint a fine line. To address this, they carefully characterized their measuring tips and included this information in their protocol, ensuring that the reported measurements are tied to the specific tool used.

By defining these measurements and the steps to take them, the researchers have provided a common language for the field. Before this work, it was difficult to say with certainty whether a rough wall was the cause of a device's poor performance or just a coincidence. Now, scientists can measure the wall's geometry with a known level of accuracy and compare it directly to how the device behaves. The data shows that while some walls are quite smooth, others have features that could theoretically contribute to energy loss. However, the researchers are careful to note that a rough surface does not automatically mean a bad device; the relationship between the shape and the performance is complex and depends on many factors. The new protocol does not solve the problem of energy loss on its own, but it provides the necessary tools to investigate it systematically. With this framework, future studies can now look for clear patterns between the microscopic geometry of the walls and the lifespan of the qubits, bringing the scientific community one step closer to building more reliable quantum computers.

Technical Summary: Sidewall Metrology Protocol for Superconducting Qubit Devices

Problem Statement
Superconducting qubits are a leading platform for scalable quantum computing, yet achieving reliable and consistent device performance remains a significant challenge. Variations in qubit performance occur even between devices with identical designs and layouts, suggesting that structural properties related to materials and fabrication processes are critical factors. Recent studies indicate that sidewall profiles and angles may influence coherence times, potentially acting as sources of dielectric loss through parasitic two-level systems (TLS) at interfaces. However, the quantitative characterization of sidewall morphology remains difficult. Existing techniques, such as cross-sectional FIB-SEM or HR-TEM, provide high-resolution 2D imaging but struggle to yield statistically representative data across entire devices. Furthermore, standard Scanning Probe Microscopy (SPM) has historically focused on lateral line-edge roughness (LER), leaving the quantitative characterization of full vertical sidewall profiles—including local angles and morphological variations—underdeveloped, particularly in the context of superconducting qubit devices.

Methodology
The authors developed a measurement framework based on Scanning Probe Microscopy (specifically Atomic Force Microscopy, AFM) to quantitatively characterize superconducting qubit sidewalls. The methodology relies on a "tilted-sample" AFM approach, where samples are mounted on a wedge (50°) to allow the probe to access vertical sidewall regions that are inaccessible in conventional non-tilted configurations.

The framework introduces specific geometrical descriptors and processing algorithms:

Lateral Sidewall Profile (LSP): Describes the lateral position of the sidewall surface. The primary descriptor is the RMS lateral sidewall roughness ( $R^LSP_q$ ), calculated as the average RMS amplitude of band-pass filtered residual profiles.
Vertical Sidewall Profile (VSP): Describes the cross-section of the vertical sidewall. Since a reference profile is unavailable for a residual amplitude descriptor, the authors propose a curvature-equivalent radius ( $R_\rho$ ). This metric is the inverse of the profile-averaged RMS curvature, weighting small radii of curvature (sharp features) more strongly. An auxiliary parameter, the minimum local radius of curvature ( $\rho_{min}$ ), is also defined.
Sidewall Detection Algorithms: Three methods were evaluated to identify the transition region between the substrate, sidewall, and top plane: a height-based method, a gradient-based method, and a cumulative gradient-based method. The height-based method was selected for its robustness and reproducibility in defining transition lengths.
Probe Characterization: Recognizing that AFM measurements are convolved with the probe tip geometry, the authors estimate an effective probe radius ( $\rho_{eff}^{probe}$ ) using a tip characterization sample. They argue that descriptors should be specified alongside the probe geometry, treating the probe as an integral part of the measurement procedure rather than attempting deconvolution for features smaller than the probe.

Key Contributions

Standardized Descriptors: The paper defines a refined RMS lateral sidewall roughness and a novel curvature-equivalent radius specifically for quantifying vertical sidewall morphology.
Measurement Protocol: A step-by-step protocol is proposed, including sample tilting, specific filtering parameters (short- and long-wavelength cutoffs), and data processing steps (leveling, filtering, and probe correction).
Uncertainty Analysis: The authors provide a comprehensive assessment of measurement variability, identifying sources such as probe-to-probe variation, probe degradation, sample inhomogeneity, and contamination. They estimate a combined measurement uncertainty ( $k=1$ ) in the range of 15–30% for the morphological descriptors.
Experimental Demonstration: The framework was applied to various components of transmon qubits, including Josephson junction electrodes, capacitor pads, and readout resonators, fabricated on both silicon and sapphire substrates.

Results
Experimental application of the protocol to seven wet-etched transmon qubit devices and additional readout resonators yielded the following observations:

Roughness Variability: The average lateral sidewall roughness ( $R^LSP_q$ ) ranged from approximately 2–5 nm for Josephson junction structures to approximately 20 nm for readout resonators. A visible local pit increased roughness to ~30 nm.
Vertical Morphology: The curvature-equivalent radius ( $R_\rho$ ) for Josephson junction electrodes ranged from 35 to 82 nm, while capacitor pads ranged from 51 to 151 nm. One capacitor pad profile exhibited a sharp protrusion with a corrected local radius of curvature of -10.9 nm.
Angle Distribution: Analysis of sidewall angle probability density functions (PDFs) revealed that sidewalls are often not straight edges with rounded corners. Instead, they display shallow, wide, and sometimes bimodal angle distributions, with significant asymmetry about the midpoint. For example, median sidewall angles varied significantly between the foot-to-midpoint and midpoint-to-top regions.
Reproducibility: Repeated measurements with the same probe showed high repeatability, while variations between different probes or measurement sessions highlighted the necessity of the proposed uncertainty framework.

Significance and Claims
The paper claims to establish a foundation for the quantitative comparison of fabrication processes across laboratories. By providing a standardized, traceable protocol with defined descriptors and uncertainty budgets, the work enables future investigations into the correlations between sidewall geometry and qubit performance.

The authors emphasize that surface roughness should not be viewed as a direct measure of superconducting quality, but rather as a proxy for microscopic film and interface properties (such as defect density, grain boundaries, and oxide chemistry) that contribute to loss mechanisms. They caution that establishing a statistically sound correlation between sidewall features and qubit lifetime requires a comprehensive understanding of various decoherence channels. The proposed protocol is intended to facilitate these future statistical studies by ensuring that sidewall measurements are reproducible and comparable, thereby helping to isolate the impact of sidewall morphology on device coherence.

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