Scalable Microring-Based Interconnects with Channel Equalization and Closed-Loop Stabilization

Technical Summary: Scalable Microring-Based Interconnects with Channel Equalization and Closed-Loop Stabilization

Problem Statement
The transition of photonic computing from isolated single-core processors to scalable, distributed multi-core systems requires an interconnect layer capable of transferring intermediate computational states entirely in the optical domain while preserving analog amplitude fidelity. Unlike digital optical links, which can tolerate moderate wavelength-dependent loss and path-dependent insertion loss as long as logic-state margins are maintained, analog photonic processors use optical power or field amplitude as computational variables. Consequently, channel-power variations caused by wavelength-dependent loss, path-dependent insertion loss, and resonance drift distort analog signals. In microring-resonator (MRR)-based interconnects, these impairments are exacerbated by sensitivity to fabrication variations, thermal crosstalk, and environmental fluctuations. When multiwavelength analog optical states are routed between distributed photonic computing units (PCUs), these power imbalances accumulate as computational errors across cascaded layers, particularly in deep neural network workloads. Existing MRR control strategies address device- or core-level stabilization but do not directly solve the interconnect-level signal-preservation problem involving wavelength-selective routing, post-routing power balancing, and drift-tolerant stabilization within a single module.

Methodology
The authors propose and experimentally demonstrate a Photonic Interconnect Unit (PIU) designed to address these challenges on a 180-nm silicon photonic platform. The PIU integrates three core components:

1. Wavelength-Selective Switching Fabric: A compact 4×4 MRR-based switching fabric utilizing a triangular mesh of six cascaded 2×2 MRR crossbar elements. This design supports reconfigurable wavelength-division multiplexing (WDM) redistribution, including multiplexing (MUX) and demultiplexing (DEMUX), with reduced hardware and control complexity compared to dense crossbar architectures.
2. Programmable Channel Equalization: A cascaded stage of programmable MRRs acting as wavelength-selective attenuators. These units trim stronger channels toward a common target power level without optical-electrical-optical conversion. By thermally detuning the resonance notch relative to the routed channel peak, the spectral overlap is adjusted to control attenuation.
3. Closed-Loop Stabilization: A three-phase Field-Programmable Gate Array (FPGA)-assisted feedback controller implementing a Proportional-Integral-Derivative (PID) locking strategy. The control sequence consists of:
   • Phase 1: Construction of a voltage-power lookup table (LUT).
   • Phase 2: Monotonic target acquisition to identify the operating region.
   • Phase 3: Real-time sign-aware PID locking to maintain the target power, compensating for resonance drift and thermal fluctuations.

Key Results
Experimental characterization and hardware-aware simulations yielded the following results:

• Routing and Equalization Performance: The PIU demonstrated reconfigurable WDM signal redistribution with crosstalk suppression exceeding 20 dB for selected DEMUX channels. The two-stage equalization suppressed residual multiwavelength channel-power variation to below 0.2 dB. The switching response time was measured at approximately 27.83 µs (rise) and 22.53 µs (fall).
• Stability and Precision: The FPGA-assisted PID controller achieved convergence within 40 ms. Using a high-resolution sourcemeter to bypass FPGA ADC resolution limits, the system demonstrated a 10.3-bit-equivalent steady-state control precision. The system maintained signal-to-noise ratio (SNR) fluctuations below 0.5 dB across a 22 °C temperature variation (18 °C to 40 °C).
• Optical Weight Reconstruction: In an eight-channel multiwavelength optical weight reconstruction task, closed-loop stabilization reduced the normalized end-to-end root-mean-square error (RMSE) from 0.179 (free-running) to 0.0193, representing a 9.3-fold error reduction.
• System-Level Impact: Hardware-aware inference simulations on VGG-11 and ResNet-18 networks using a measurement-derived 6.5-dB channel-mismatch model showed that without equalization, ResNet-18 accuracy dropped to 54.33%. With PIU equalization, accuracy was recovered to approximately 94.6%, matching the clean hardware-reference level. Similarly, VGG-11 accuracy was restored from 66.97% to ~92.9%.

Significance and Claims
The paper establishes the PIU as an actively stabilized analog signal-conditioning layer rather than a passive optical routing fabric. The authors claim that by co-designing routing reconfigurability, post-routing equalization, and drift-tolerant stabilization in a single unit, the PIU directly addresses a key scaling bottleneck in distributed photonic computing: the requirement for intermediate optical signals to remain in the analog domain while maintaining sufficient amplitude fidelity for downstream computation.

The work demonstrates that interconnect-level equalization and stabilization are essential for preserving analog optical states in distributed photonic computing clusters. The authors position the PIU as a practical route toward reconfigurable multi-core photonic systems where optical signals can be routed between computing units without the accumulation of computational errors caused by channel-power imbalance. The study highlights that while shared optical gain (e.g., SOAs) can provide coarse power recovery, fine, wavelength-selective channel-power balancing via the PIU is necessary to correct wavelength- and route-dependent imbalances. The results suggest that such active interconnects are a prerequisite for realizing the full potential of scalable, multi-core photonic computing architectures.