Technical Summary: Wavelength-Division-Multiplexed Photonic Tensor Core Using Nonvolatile and Volatile Weighting

Problem Statement

As artificial intelligence models scale to hundreds of billions of parameters, digital electronics face limitations in transistor scalability and energy efficiency, struggling to meet the throughput demands of growing token usage. While optical interconnects are advancing toward co-packaged and near-packaged optics, there remains a need to determine if photonic integrated circuits (PICs) can provide computational benefits for tensor operations, which constitute a large fraction of transformer workloads. Existing photonic tensor cores (PTCs) often target specific tasks (inference or training) or utilize isolated technologies (either non-volatile phase-change materials or active thermo-optic modulators) without a unified, experimentally validated architecture that supports both weighting regimes, on-chip accumulation, and a custom compiler for general matrix multiplication.

Methodology

The authors designed, taped out, packaged, and demonstrated a modular Wavelength-Division-Multiplexed (WDM) photonic tensor core architecture. The system utilizes a power-scaled silicon photonic chip where an array of lasers encodes input vector values, which are multiplexed and distributed to PTC modules.

The research focuses on two distinct hardware implementations of the weighting mechanism within the same WDM architecture:

1. Nonvolatile Weighting (P-RAM): Utilizing Phase-Change Material (GSSe) to create Photonic Random Access Memory. This implementation leverages the amorphous and crystalline states of the material for ultra-low power, passive weighting suitable for edge computing and infrequently updated model parameters. The device encodes multi-level weights (demonstrated as 2-bit/4-level precision) via intensity modulation.
2. Volatile/Active Weighting (Thermo-optic MZI): Utilizing Mach-Zehnder Interferometers (MZIs) with integrated heaters for rapidly reconfigurable matrix operations. This implementation targets training tasks or dynamic inference, offering high extinction ratios (>20 dB) and high-speed reconfiguration.

Key System Components:

• WDM Multiplexing/Demultiplexing: Passive add-drop microrings distribute and recombine multiple wavelength channels (e.g., 1548.1, 1550.2, 1551.5 nm).
• Accumulation: The architecture employs photodetectors to perform the accumulation (summation) of the multiply-accumulate (MAC) operations. The study compares two configurations: one with on-chip photodiodes for accumulation and another with off-chip (external) photodiodes.
• General Matrix-Multiply (GeMM) Compiler: A custom compiler was developed to partition large matrices into submatrices compatible with the physical dimensions of the fabricated PTC prototypes (e.g., 3x3). This allows the system to handle image processing and larger neural network tasks by spatially down-sampling inputs.

Key Contributions

• Separate Implementation of Weighting Technologies: The paper presents the experimental demonstration of a modular WDM-based PTC architecture validated across both non-volatile (GSSe PCM) and active (MZI) physical weighting implementations. Notably, these two weighting technologies were implemented and evaluated separately rather than simultaneously integrated into a single optical path.
• Dual-Mode Implementation: The authors successfully fabricated and characterized two distinct PTC modules: one using PCM/P-RAM for nonvolatile storage (evaluated with off-chip accumulation) and another using thermo-optic MZIs for active weighting (evaluated with both on-chip and off-chip accumulation).
• Hardware-Aware Emulation: The study introduces a workflow where a GeMM compiler partitions tasks, and experimentally measured MZI transfer maps are used to emulate hardware-aware inference, accounting for real-world non-idealities like noise and precision limits.
• System-Level Integration: The work consolidates signal parallelism via WDM, robust amplitude weighting schemes, and linear-scaling modular design into a single platform, moving beyond isolated device demonstrations.

Results

• Nonvolatile P-RAM Performance: The PCM-based module demonstrated 4-level weight encoding (2-bit precision) with ultra-low power consumption. Over 10,000 MAC operations, the module achieved a mean error of 0.0016 and a standard deviation of 0.019.
• Active MZI Performance: The thermo-optic MZI implementation achieved an extinction ratio greater than 20 dB. Calibration using power maps revealed approximately 6 Equivalent Number of Bits (ENOB) precision for the weighting scheme. Integrated photodiodes provided a response closer to the ideal case compared to optical I/O, reducing noise and instability.
• Image Processing: The MZI-based PTC was used to perform edge detection and augmented reality (AR) image composition on a George Washington University logo.
  • Edge detection yielded an experimental error rate of 3.41% (compared to 1.1% in hardware-aware emulation).
  • AR mask generation (combining a face and a mask) achieved an error rate of 0.3%.
• Machine Learning Inference: Using the MNIST dataset, the authors compared a fully electronic GPU, a fully photonic PTC, and a hybrid approach.
  • The hybrid approach (PTC for convolution layers, GPU for non-linearities and fully connected layers) achieved the best Figure-of-Merit (FOM), improving performance by over 100% compared to other solutions.
  • The fully photonic approach showed slight accuracy reductions in fully connected layers due to hardware non-idealities but offered significant gains in latency and energy efficiency for linear operations.
• Scalability Projections: Under scaling assumptions, a projected 9×9 implementation is estimated to reach 8.75 tera-operations per second (TOPS) and 3.04 TOPS/W, including data-conversion overheads.

Significance and Claims

The paper claims that this work bridges the gap between theoretical photonic computing models and practical, system-level implementation. By demonstrating a modular architecture that supports both nonvolatile and volatile weighting (evaluated separately), the authors show that photonic tensor cores can be adapted to different application regimes (edge inference vs. data center training).

The significance lies in the ability to perform linear multiply-accumulate operations entirely on-chip with high energy efficiency and low latency, avoiding the energy costs of domain crossings between optical and electronic domains. The authors posit that this technology enables "extreme edge computing" and supports Industry 4.0 applications by offering compact, high-throughput solutions for size-weight-area-power (SWAP) constrained environments.

The authors remain modest regarding current limitations, noting that the current 3×3 prototype is limited to 0.32 TOPS and that the demonstrated accuracy improvements rely on hybrid architectures where non-linear operations remain electronic. They acknowledge that future work requires integrating non-linear and pooling operations optically to unlock the full potential of PTCs and that practical deployment will require thermal stabilization and active tuning of microring resonators.