⚡ electrical engineering

Running orbital AI data centers hot: chip leakage matters as much as temperature tolerance

This study demonstrates that for orbital AI data centers, minimizing chip leakage is as critical as increasing temperature ratings for mass reduction, because current leakage levels largely negate the mass savings expected from operating at higher temperatures, though improved thermal management can still yield significant gains.

Original authors: Jiawei Jing

Published 2026-10-26

📖 5 min read🧠 Deep dive

CC BY 4.0

Original authors: Jiawei Jing

Original paper licensed under CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine trying to build a supercomputer in space. The goal is to train massive artificial intelligence models while orbiting Earth, but there is a fundamental physical problem: computers generate heat, and in the vacuum of space, there is no air to blow that heat away. The only way to cool a machine in orbit is to radiate it out into the cold darkness of deep space using large, flat panels called radiators. The hotter these panels can get, the smaller they can be, because heat radiation grows incredibly fast as temperature rises. This simple physical rule has led engineers to propose running orbital data centers at scorching temperatures, hoping to shrink the heavy radiators down to a manageable size.

However, a new study suggests that this plan hits a hidden wall. While the radiators might get smaller, the computer chips inside the machine behave differently when they get hot. As silicon chips warm up, they begin to "leak" electricity, wasting power even when they are not doing any work. This wasted power turns into more heat, which makes the chips even hotter, which causes even more leakage. It is a vicious cycle. The research shows that for the current generation of computer chips, this leakage is so powerful that it cancels out almost all the benefits of running the system hot. The idea that simply making chips that can withstand higher temperatures would solve the mass problem is, according to this analysis, largely an illusion.

The researcher, Jiawei Jing of the Makuhari Development Corporation in Japan, built a detailed computer model of a liquid-cooled satellite designed to be an orbital AI data center. They treated the entire system as a single, connected machine. In their model, the chips are cooled by a liquid that flows through pipes, carrying heat away to the radiator panels. The team then ran thousands of simulations, changing the maximum temperature the chips and their memory could handle, and watching how the total weight of the satellite changed. They included every major component: the solar panels needed to generate electricity, the batteries to store it, the pumps to move the coolant, and the radiators to dump the heat. Crucially, they did not treat the chips as static objects; they programmed the model to account for the fact that as the chips get hotter, they leak more electricity and consume more power.

The results were stark. The literature on orbital data centers often suggests running radiators at temperatures between 350 and 385 Kelvin (roughly 80 to 110 degrees Celsius) to minimize their size. To achieve this, the chips themselves would need to operate at temperatures between 117 and 174 degrees Celsius. The study found that if you could magically build chips that never leaked electricity, raising their temperature limit from the current 85 degrees to 150 degrees would indeed save about 23.5 percent of the satellite's total mass. But real chips do leak. When the researchers plugged in the actual leakage rates of today's most powerful graphics processing units, the savings evaporated. The extra heat generated by the leakage forced the system to carry larger solar panels and bigger radiators just to handle the waste, effectively undoing the gains. In the end, the mass savings dropped from 23.5 percent down to a mere 2.6 percent.

The study also explored whether the system could even remain stable at these high temperatures. Because leakage increases so sharply with heat, there is a point where the chip produces more heat than the cooling system can remove, leading to a runaway effect where the chip destroys itself. The simulations showed that for the proposed high-temperature designs, most current chip behaviors would lead to this instability unless the temperature difference between the chip and the cooling liquid was drastically reduced. In other words, simply making chips that can survive higher heat is not enough; the physics of leakage makes the system unstable before it can reach the desired efficiency.

So, if running the chips hotter is a dead end, what is the solution? The researchers found a different lever to pull. Instead of making the chips hotter, they proposed making the cooling system more efficient at removing heat from the chips. Currently, there is a large temperature gap between the hot chip and the cooler liquid flowing past it, much like a thick winter coat trapping body heat. The study showed that by improving the thermal connection—using better materials or designs to shrink this gap—the liquid coolant could be allowed to run much hotter without actually heating the chips themselves. This allows the radiators to operate at high temperatures and stay small, while the chips remain cool enough to avoid the worst of the leakage.

This approach of "bypassing" the leakage problem proved far more effective than trying to tolerate higher temperatures. By reducing the temperature gap between the chip and the coolant from 40 degrees to 25 degrees, the model showed a mass saving of nearly 8 percent. This is more than three times the saving achieved by simply raising the temperature limits of the chips. The key insight is that the bottleneck is not the chip's ability to survive heat, but the system's ability to keep the chip cool while the radiator gets hot. The study concludes that for orbital AI data centers to be feasible, chip designers must focus just as much on minimizing electrical leakage as they do on increasing temperature tolerance. The path to a lighter, more efficient space computer lies not in building hotter machines, but in building better cooling systems that keep the chips cool while the rest of the satellite runs hot.

Technical Summary: Running Orbital AI Data Centers Hot

Problem Statement
Proposals for orbital AI data centers (2024–2026) suggest placing radiators at high temperatures (350–385 K) to exploit the Stefan–Boltzmann fourth-power law, thereby minimizing radiator mass. However, existing literature often treats the radiator temperature as an independent input, overlooking the coupling between chip temperature and power consumption. In terrestrial data centers, higher temperatures increase leakage current, raising power draw and cooling energy. In orbit, where mass is the primary constraint and the radiator is the sole heat sink, this coupling creates a critical trade-off: raising the radiator temperature requires hotter coolant, which forces chips and High-Bandwidth Memory (HBM) to operate at higher junction temperatures. This increase in temperature drives up leakage power, necessitating larger solar arrays and radiators to reject the additional heat. The central question addressed is whether the mass savings from a smaller radiator are negated by the mass penalties of increased leakage power, and if current leakage levels prevent the realization of high-temperature designs.

Methodology
The study develops a closed-loop on-orbit mass model for a liquid-cooled compute satellite. The model integrates:

Thermal-Electrical Coupling: A fixed-point equation solving for junction temperature ( $T_j$ ) based on coolant temperature ( $T_c$ ) and normalized chip power ( $\Psi$ ), where $\Psi$ increases with $T_j$ due to leakage.
Leakage Modeling: Chip power is split into dynamic and leakage components. Leakage is modeled using an Arrhenius-type function ( $T^2 e^{-E_a/kT}$ ), constrained by vendor power-estimation tools (TSMC, AMD) and transistor measurements. The leakage fraction ( $P_L$ ) and activation temperature ( $E_a$ ) are derived from data-center GPU telemetry (H100, V100) and fitted to three "shapes" (flat, median, steep).
System Mass Components: The total mass per kW of reference compute ( $kW_{ref}$ ) includes compute hardware, fixed mass, radiator mass (dependent on area and temperature), solar array mass (dependent on total bus power), energy storage, and heat-pump mass (if applicable).
Design Variables: The study treats chip and HBM temperature limits as design variables (scanned from 85/95 °C to 150 °C) and analyzes the impact of the "temperature stack" (the difference between junction/HBM and coolant temperatures).
Verification: The model is validated against published estimates from Turyshev and the Starcloud white paper, as well as hardware anchors like the ISS photovoltaic radiator and NASA Glenn Research Center tests.

Key Contributions and Results

Chip Requirements for Literature Temperatures:
To achieve the literature-suggested effective radiating temperatures of 350–385 K, the study finds that chip and HBM temperature limits must be raised to approximately 117–174 °C. However, at these temperatures, present leakage levels destabilize the thermal loop. For a nominal radiator, a design targeting 350 K is only stable if the leakage activation temperature is below ~2750 K (flat shape); the median and steep shapes (representing current GPU behavior) result in no stable operating point at nominal clock speeds, implying that such designs would require permanent clock throttling.
Leakage Cancels Mass Savings:
Raising chip and HBM limits from 85/95 °C to 150 °C would theoretically save 23.5% of on-orbit mass for a chip with zero leakage. However, with present leakage levels ( $P_L \approx 0.15$ ), this saving is reduced to just 2.6% for a nominal radiator. Leakage cancels approximately 90% of the potential mass reduction. The mechanism is that the extra leakage power requires a larger solar array and radiator, which offsets the area reduction gained from higher temperatures.
Break-Even Leakage Thresholds:
The study quantifies the "leakage-driven power growth" ( $\delta$ , % K⁻¹) required for higher ratings to be beneficial. The break-even value ( $\delta_0$ ) scales linearly with the radiator's share of the power-dependent mass ( $\hat{U}_{eff}$ ). For a nominal radiator, $\delta_0 \approx 0.80\% \text{ K}^{-1}$ . Present GPUs exhibit $\delta \approx 0.42–0.51\% \text{ K}^{-1}$ , which is below the break-even point (allowing some savings) but well above the threshold required for a 5% mass saving ( $\delta_5 \approx 0.33\% \text{ K}^{-1}$ ).
Bypassing Leakage via Temperature Stack Reduction:
The most effective strategy identified is not raising temperature limits, but reducing the temperature stack (the difference between junction/HBM and coolant). Reducing both chip-to-coolant and HBM-to-coolant differences from 40 K to 25 K allows the coolant to run 15 K hotter without increasing chip temperatures. This bypasses the leakage penalty entirely.
- Result: This approach saves 8.0% of on-orbit mass with a nominal radiator, nearly independent of leakage levels.
- Comparison: This saving (8.0%) significantly exceeds the saving from raising temperature limits under present leakage conditions (2.6%).
Alternative Approaches:
- Clock Scaling: Lowering the clock reduces power and leakage, saving ~25% mass, but requires ~39% more chips, making it cost-prohibitive unless chip prices are extremely low relative to launch costs.
- Heat Pumps: Using a heat pump to raise radiator temperature without heating chips adds compressor mass and power. For nominal radiators, this increases total mass by 4.7–35.7%; it only yields savings with very heavy radiators.

Significance and Claims
The paper claims that for orbital AI data centers, low leakage is as critical a specification as high temperature tolerance. The study concludes that simply qualifying chips for higher temperatures (e.g., 150 °C) will not yield significant mass savings unless leakage is simultaneously reduced.

The primary design lever for mass optimization is not the absolute temperature limit, but the temperature stack. Reducing the thermal resistance between the chip/HBM and the coolant offers a more reliable path to mass reduction than increasing temperature ratings, as it avoids the compounding penalty of leakage power. The author asserts that future chip specifications for space should prioritize leakage-driven power growth ( $\delta$ ) alongside junction temperature ratings, and that radiator temperatures should be determined by these chip specifications and the system's radiator mass share, rather than being set a priori based on the fourth-power law alone.

Technical Summary: Running Orbital AI Data Centers Hot

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