Simultaneous Multi-die Floorplanning and Technology Assignment

1. Problem Definition: SMUFTA

The paper addresses the Simultaneous Multi-die Floorplanning and Technology Assignment (SMUFTA) problem, a critical challenge in heterogeneous integration (2.5D chiplets and 3D ICs).

• The Core Challenge: Traditional floorplanning assumes fixed block technologies and dimensions. However, in heterogeneous systems, different dies may use distinct manufacturing nodes (e.g., 7nm, 45nm). Pre-assigning blocks to specific technologies is suboptimal because it ignores the complex interplay between technology choice, interconnect wirelength, timing, power, and cost.
• The "Chicken-and-Egg" Dilemma: Determining the optimal floorplan requires knowing the block sizes (which depend on technology), but determining the optimal technology assignment requires knowing the floorplan constraints.
• Objective: The goal is to simultaneously assign circuit blocks to specific dies, determine their aspect ratios, and optimize their physical locations to minimize a composite cost function ($f$) comprising:
  • Wirelength ($W$): Total Half-Perimeter Wire-Length (HPWL), including intra-die and inter-die (interposer or TSV) connections.
  • Power ($P$): Total dynamic power.
  • Cost ($C$): Manufacturing cost derived from a yield model.
  • Timing ($T$): Total Negative Slack (TNS).
• Constraints:
  • Die area limits ($A_{min} \le A(d_i) \le A_{max}$).
  • Maximum number of inter-die nets ($N_{max}$).
  • TSV feasibility in 3D ICs (ensuring space for vertical connections).

2. Methodology

The proposed SMUFTA framework employs a four-phase iterative optimization process, leveraging Machine Learning (ML) for rapid PPA (Power, Performance, Area) estimation.

A. PPA Estimation via Machine Learning

Instead of running time-consuming synthesis and place-and-route (P&R) tools for every iteration, the system uses XGBoost-based ML models (trained on post-placement data) to estimate PPA metrics for circuit blocks based on their assigned technology and aspect ratio. This allows for rapid evaluation during the optimization loop.

B. The Four-Phase Optimization Flow

1. Phase I: Initial Die Assignment

   • Blocks are assigned to dies based on an estimated average die area.
   • Blocks are sorted by size (assuming the oldest technology) and assigned to dies sorted by technology node (newest to oldest).
   • Block aspect ratios are refined to minimize a partial objective (Power + TNS) using the ML models.

2. Phase II: Intra-Die Floorplanning

   • Blocks assigned to a specific die are placed using a B-tree representation* (efficient for non-slicing floorplans).
   • Three optimization techniques are evaluated for this phase:
     • Simulated Annealing (SA): Uses standard perturbations (swap, remove-insert, aspect ratio change, rotation).
     • Bayesian Optimization (BO): Uses a Gaussian Process surrogate model to guide the search efficiently.
     • Reinforcement Learning (RL): Uses Proximal Policy Optimization (PPO). A dedicated RL agent is trained for each die to learn technology-specific placement strategies. The state space is defined by B*-tree features (node height, cumulative children, HPWL).

3. Phase III: Inter-Die Refinement

   • To escape local optima, blocks are periodically reassigned between dies.
   • This step interleaves greedy selection (choosing the block that maximizes objective improvement) and random selection (to encourage exploration).
   • Reassignments are only accepted if they satisfy die area constraints.

4. Phase IV: TSV Feasibility Enforcement (3D ICs only)

   • Ensures sufficient space exists for Through-Silicon Vias (TSVs) connecting vertically stacked dies.
   • Calculates TSV area demand and allocates "white space" within blocks or at block boundaries if internal empty space is insufficient.

3. Key Contributions

• First Systematic Study: This is the first work to treat technology assignment as a variable within multi-die floorplanning, addressing a major gap in heterogeneous integration research.
• Solution to the Coupling Problem: It provides a systematic approach to resolve the "chicken-and-egg" dilemma between floorplanning and technology selection.
• ML-Integrated Optimization: It integrates ML-based PPA estimation directly into the optimization loop, enabling the evaluation of a vast solution space that would be computationally prohibitive with traditional EDA tools.
• RL for Multi-Die Systems: It introduces a multi-agent RL approach where each die has a dedicated agent, proving superior to single-agent or random-search methods in handling technology-specific constraints.
• Validation: The method is validated using commercial tools (Synopsys Design Compiler, Cadence Innovus, Cadence Integrity) for both 2.5D and 3D ICs, ensuring industrial relevance.

4. Experimental Results

The authors evaluated the method on six benchmarks (including OpenPiton and IWLS 2005 designs) using 45nm and 7nm technologies.

• Performance vs. Baseline: Compared to a greedy baseline (hMetis partitioning + SA floorplanning), the SMUFTA-RL approach achieved the best results:
  • 2.5D Chiplets: ~11.6% improvement in timing (TNS), 9% reduction in power, 9.6% reduction in area, and 6.7% reduction in cost.
  • 3D ICs: ~13.3% improvement in timing, 7.7% reduction in power, and 8.9% reduction in area, while maintaining TSV feasibility.
• Comparison of Techniques:
  • RL consistently outperformed SA and BO in solution quality.
  • Runtime: While RL had higher runtime than SA in some cases, it was often faster than BO. Notably, for 4-die configurations, RL was 0.94x faster than the baseline while delivering better quality.
• Hard IPs: The method successfully handled "Hard IPs" (blocks with fixed technology), still achieving significant improvements (e.g., 12.8% timing improvement) over the baseline.
• Ablation Studies:
  • Refinement Frequency ($K$): An optimal refinement frequency of $K=20$ was found; too frequent or too infrequent refinement degraded results.
  • Agent Architecture: Using a dedicated agent per die was crucial; a single-agent approach failed to converge, highlighting the need to capture die-specific technology nuances.

5. Significance

This work fundamentally shifts the paradigm of heterogeneous IC design. By demonstrating that simultaneous optimization of floorplanning and technology assignment yields significantly better PPAC (Performance, Power, Area, Cost) results than sequential or greedy approaches, it provides a blueprint for future 2.5D/3D design automation. The integration of ML for rapid estimation and RL for complex decision-making offers a scalable path forward for designing increasingly complex chiplet-based systems. Future work aims to extend this framework to include thermal management and mechanical warpage constraints.