💻 computer science

Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security

This paper presents Crypto-RV, a high-efficiency FPGA-based RISC-V co-processor that unifies support for diverse cryptographic algorithms within a single 64-bit datapath, achieving significant speedups and energy efficiency improvements over baseline cores and CPUs to secure resource-constrained IoT environments.

Original authors: Anh Kiet Pham, Van Truong Vo, Vu Trung Duong Le, Tuan Hai Vu, Hoai Luan Pham, Van Tinh Nguyen, Yasuhiko Nakashima

Published 2026-02-05

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CC BY 4.0

Original authors: Anh Kiet Pham, Van Truong Vo, Vu Trung Duong Le, Tuan Hai Vu, Hoai Luan Pham, Van Tinh Nguyen, Yasuhiko Nakashima

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine your computer or smart device is a busy kitchen. In this kitchen, the Chef (the main processor) is trying to prepare a complex meal, but a huge part of the job involves constantly running to the pantry to grab ingredients, chopping them, and then running back to the pantry to store the leftovers. This "running back and forth" takes up most of the time, leaving the actual cooking to happen very slowly.

In the world of digital security, this "cooking" is called cryptography. It's the process of scrambling data to keep it safe (like locking a diary) or checking if a message has been tampered with (like a wax seal on a letter). Currently, many devices (especially small ones like IoT sensors) are slow at this because they keep running back and forth to their "pantry" (memory) to get the data they need.

Crypto-RV is a new, super-efficient "specialized sous-chef" designed to fix this problem. Here is how it works, using simple analogies:

1. The Problem: The "Pantry Run" Bottleneck

In standard devices, when the main processor needs to do a security check, it has to:

Go to memory to get a chunk of data.
Do a math operation.
Go back to memory to save the result.
Repeat this hundreds of times.

The paper explains that 70% to 85% of the time is wasted just moving data, not actually doing the math. It's like a chef who spends 10 minutes walking to the fridge and 1 minute chopping an onion.

2. The Solution: The "All-in-One" Counter (Crypto-RV)

The researchers built a special co-processor called Crypto-RV. Think of this as a dedicated counter right next to the stove that holds everything the chef needs for the entire recipe.

The Big Buffer (The Counter): Instead of running to the pantry, Crypto-RV has a massive, high-speed internal counter (a 128x64-bit buffer). It loads all the necessary ingredients (data and constants) once at the start. Then, it keeps all the intermediate steps right on the counter. The chef never has to leave the stove.
The Specialized Tools (The Engines): Instead of using one generic knife for everything, Crypto-RV has specialized tools built right into the counter. It has specific engines for different types of security "recipes":
- SHA-2 & SHA-3 & SM3: These are like different types of "hashing" (creating a unique fingerprint for data). The new design unifies these so one set of tools can handle all of them efficiently.
- AES: This is for locking and unlocking data (encryption).
- HARAKA: This is a newer, lighter tool designed for future "quantum-proof" security (protecting against super-fast future computers).

3. The "Double-Buffer" Trick (The Assembly Line)

Even with the counter, if you have a huge amount of data (like a whole truckload of vegetables), you still need to keep the counter full while you work.

Crypto-RV uses a Double-Buffering system. Imagine two buckets:

Bucket A is being used by the chef to cook right now.
Bucket B is being filled by a delivery truck (DMA) with the next batch of ingredients.

As soon as the chef finishes Bucket A, they instantly switch to Bucket B, while the delivery truck fills up a fresh Bucket A. This means the chef never stops cooking waiting for ingredients. The paper claims this makes the process continuous and eliminates the "waiting for the pantry" problem.

4. The Results: Speed and Efficiency

The researchers tested this on a chip (FPGA) and compared it to:

Standard RISC-V processors (the basic kitchen).
Powerful CPUs (like the ones in high-end laptops and servers).

The findings were impressive:

Speed: Crypto-RV is 165 to 1,061 times faster than a standard processor at doing these security tasks.
Energy: It is 5.8 to 17.4 times more energy-efficient than powerful CPUs. This is huge for battery-powered devices like smart sensors or IoT gadgets.
Size: Despite doing all this, it fits into a very small space on a chip (using only about 34,000 tiny logic blocks), making it perfect for small devices.

Summary

Crypto-RV is a specialized hardware assistant for RISC-V computers. It solves the problem of "running back and forth" to memory by keeping all data close at hand on a high-speed internal counter. It uses specialized tools to handle many different security algorithms at once and uses a "two-bucket" system to ensure it never stops working. The result is a device that secures data incredibly fast while using very little power, making it ideal for the Internet of Things (IoT) and edge computing.

Technical Summary of Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor

Problem Statement
Cryptographic operations are essential for securing IoT, edge computing, and autonomous systems. However, existing RISC-V platforms suffer from a lack of efficient hardware support for comprehensive cryptographic algorithm families, particularly when integrating post-quantum cryptography (PQC). Current solutions face significant limitations: instruction-set extensions often remain at the ISA level without concrete microarchitectures; software-optimized implementations share generic pipelines that limit multi-algorithm throughput; and existing hardware accelerators either lack tight CPU integration, support only a narrow set of 32-bit algorithms, or fail to optimize scheduling for large-hash and tree-hash workloads. Furthermore, conventional RISC-V cores experience severe memory bottlenecks during cryptographic kernels, where 70–85% of execution cycles are consumed by load/store operations rather than computation, a problem exacerbated by multi-hash workloads like Merkle trees and SPHINCS+.

Methodology and Architecture
The paper proposes Crypto-RV, a high-efficiency RISC-V co-processor designed to unify support for SHA-256, SHA-512, SM3, SHA3-256, SHAKE-128, SHAKE-256, AES-128, HARAKA-256, and HARAKA-512 within a single 64-bit datapath. Implemented on a Xilinx ZCU102 FPGA, the system integrates a Processing System (PS) with an ARM Cortex-A53 CPU and a Programmable Logic (PL) hosting the co-processor.

The architecture relies on three primary innovations:

High-Bandwidth Internal Buffer (128×64-bit): To address memory bottlenecks, Crypto-RV employs a tightly coupled internal buffer. Instead of repeatedly accessing off-chip memory for intermediate states and message blocks, the processor initializes the buffer once with constants and message words. This allows intermediate states to remain on-chip throughout the round sequence. Custom data-movement instructions facilitate bulk transfers of up to 128 words, decoupling high-bandwidth intra-round data reuse from low-bandwidth off-chip accesses. This reduces load/store instruction counts and enables crypto-specialized units to achieve one pipeline iteration per cycle after warm-up.
Cryptography-Specialized Execution Units: The co-processor utilizes unified, pipelined engines to share functional resources across multiple algorithms while maintaining a short critical path:
- Unified SM3/SHA-256/SHA-512 Unit: A four-stage pipeline sharing adders and mode-select multiplexers. In SHA-512 mode, it processes one 1024-bit block per cycle; in SHA-256/SM3 mode, the 32-bit datapath processes two blocks in parallel, effectively doubling throughput while sharing over 80% of arithmetic resources.
- Unified AES-128/HARAKA-256/512 Unit: A four-stage pipeline that accelerates full Haraka computations, including the generation of round constants (RC) from seed keys (SK) and public keys (PK). This eliminates the RC bottleneck that plagues partial implementations, enabling full acceleration for hash-based signatures like SPHINCS+.
- Unified SHA3-256/SHAKE-128/256 Unit: A two-stage unrolled structure that processes two consecutive Keccak rounds per clock cycle. This reduces the effective iteration depth from 24 to 12 rounds, halving latency compared to single-round designs while preserving timing closure at 160 MHz.
Double-Buffering Mechanism: To overcome the throughput mismatch between specialized cores and memory subsystems, Crypto-RV implements a hierarchical double-buffering scheme between a 1024×64-bit Data Memory (DM) and the 128×64-bit internal Buffer. This allows fresh data to stream into the buffer via DMA while computation proceeds on the current block, achieving perfect compute-DMA overlap ( $T_{total} \approx T_{compute}$ ). This supports continuous multi-block hashing and many-hash workloads without stalling the pipeline.

Experimental Results
Crypto-RV was implemented on the Xilinx ZCU102 FPGA operating at 160 MHz with a dynamic power consumption of 0.851 W. The design occupies 34,704 LUTs, 37,329 FFs, and 22 BRAMs.

Speedup over Baseline: Compared to a baseline RISC-V core, Crypto-RV achieves speedups ranging from 165× to 1,061×. Specifically, SHA-256/512/SM3 see improvements of 660×/604×/789×, while AES-128 and HARAKA-256/512 reach gains of 965×/1,061×/780×.
Energy Efficiency: When compared to powerful CPUs (Intel i9-10940X, Intel i7-12700H, and ARM Cortex-A53), Crypto-RV demonstrates superior energy efficiency (measured in Mbps/W). It achieves 5.8× to 17.4× better efficiency than the Intel i9-10940X, with SHA-512 reaching a peak of 11.8× improvement (187.08 Mbps/W vs. 15.89 Mbps/W).
Comparison with Prior RISC-V Works: Crypto-RV significantly reduces cycles per byte compared to related RISC-V accelerators. For instance, it is 56.70× faster than reference design [11] for SHA-256 and up to 1,291× faster for SHA-512 compared to design [13]. It consistently achieves 2.0 to 4.1 cycles/byte across all supported algorithms.

Significance and Claims
The paper claims that Crypto-RV provides a viable, high-performance, and energy-efficient solution for cryptographic processing in resource-constrained IoT environments. By unifying support for standard hash functions, block ciphers, and post-quantum primitives (HARAKA) in a single 64-bit datapath, the architecture transforms cryptographic operations from memory-bound to compute-bound execution. The authors assert that the design's ability to handle large-hash and tree-hash operations without memory stalls makes it particularly suitable for emerging PQC applications. Furthermore, the paper positions Crypto-RV as a flexible hardware platform that can be extended in future work to fully accelerate SPHINCS+ signature generation through specialized tree-hash cores, establishing a foundation for quantum-safe IoT security.