🌀 nonlinear sciences

Physical Analogue Kolmogorov-Arnold Networks based on Reconfigurable Nonlinear-Processing Units

This paper presents a scalable, hardware-native physical analogue Kolmogorov-Arnold Network (aKAN) architecture utilizing reconfigurable nonlinear-processing units (RNPUs) that achieves significant reductions in energy, latency, and area compared to digital multilayer perceptrons while maintaining accurate function approximation for edge inference.

Original authors: Manuel Escudero, Mohamadreza Zolfagharinejad, Sjoerd van den Belt, Nikolaos Alachiotis, Wilfred G. van der Wiel

Published 2026-06-30

📖 4 min read☕ Coffee break read

CC BY 4.0

Original authors: Manuel Escudero, Mohamadreza Zolfagharinejad, Sjoerd van den Belt, Nikolaos Alachiotis, Wilfred G. van der Wiel

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to teach a computer to recognize patterns, like distinguishing a cat from a dog or predicting the weather. For decades, the standard way to do this has been using "Multilayer Perceptrons" (MLPs). Think of an MLP like a massive assembly line in a factory. First, a huge team of workers (linear layers) does simple math—adding and multiplying numbers together. Then, a separate, rigid supervisor (a fixed activation function) looks at the result and decides, "Okay, this is a 'yes' or a 'no'." The problem is that this assembly line is huge, energy-hungry, and the supervisor is stuck doing the exact same thing every time, no matter the job.

The paper you shared introduces a new, smarter way to build these computers using Physical Analogue Kolmogorov-Arnold Networks (aKANs). Here is how they work, explained simply:

1. The "Smart Paint" Instead of the Assembly Line

Instead of a long assembly line where math happens first and then a decision is made, the authors built a system where the math and the decision happen at the same time, inside the material itself.

They use tiny silicon chips called Reconfigurable Nonlinear-Processing Units (RNPUs).

The Analogy: Imagine a standard light switch. It's either ON or OFF. Now, imagine a "smart dimmer" that doesn't just turn on or off, but changes its brightness and color based on how hard you press the button and how you twist a separate dial.
The Reality: An RNPU is a microscopic silicon device. You feed it an input voltage (the "button press"), and you can tune its behavior by adjusting control voltages (the "dials"). The device physically transforms the electricity into a complex, curved shape right inside the silicon. It doesn't calculate the curve; it is the curve.

2. The "Chameleon" Edge

In traditional networks, the "edges" (the connections between neurons) just carry numbers. In this new system, the edges are chameleons.

The authors connect several of these "smart dimmers" (RNPUs) together to form an Edge Processor.
By mixing and matching these units, they can create almost any shape of mathematical function they need. If the task requires a wavy line, the silicon bends to make a wave. If it needs a sharp spike, the silicon bends to make a spike.
This is like having a sculptor who can instantly reshape clay into any form needed, rather than having a factory that only produces pre-made bricks.

3. Why It's a Big Deal (The Energy and Space Savings)

The paper tested this new system against the old "assembly line" style computers.

The Result: To do the same job (like predicting a curve or sorting data), the new system used 100 times less energy and took up 10 times less space on a computer chip.
The Metaphor: If the old computer was a massive, gas-guzzling truck delivering a single package, this new system is a lightweight, electric bicycle delivering the same package. It gets the job done with a tiny fraction of the fuel and road space.

4. How They Tested It

The researchers didn't just simulate this on a computer; they actually built it with real silicon devices.

They trained the system using software to figure out the perfect settings for the "dials" (control voltages) on the silicon chips.
Then, they tested it on real hardware. They used it to fit complex curves (like sine waves and Bessel functions) and to sort data (like telling if a spiral pattern was turning left or right).
Key Finding: Even though the silicon chips were slightly different from each other (like how every hand is slightly different), the system was robust. It could still learn and adapt, proving that this "physical computing" approach is reliable.

5. The "Pruning" Trick

One clever feature they demonstrated is pruning.

Imagine you have a team of 100 sculptors, but you only need 5 to make a statue. The system can automatically identify which sculptors aren't doing much work and "turn them off."
This makes the final device even smaller and more efficient, removing the unnecessary parts without losing the ability to solve the problem.

Summary

The paper claims that by moving away from rigid, digital math and instead using the natural, physical properties of silicon to do the heavy lifting, we can build neural networks that are:

Tiny: Much smaller than current chips.
Efficient: Using a fraction of the battery power.
Flexible: The "edges" of the network can change their shape to fit the specific problem, rather than being stuck with a one-size-fits-all approach.

This opens the door to putting powerful AI directly into small, battery-powered devices (like sensors or wearables) without needing a massive data center to do the thinking.

Technical Summary: Physical Analogue Kolmogorov-Arnold Networks based on Reconfigurable Nonlinear-Processing Units

Problem Statement
Modern deep learning relies heavily on Multilayer Perceptrons (MLPs), which perform linear matrix-vector multiplications followed by fixed nonlinear activation functions. While linear operations are efficiently accelerated in current digital and mixed-signal hardware (e.g., GPUs, memristive crossbars), the nonlinear activation functions remain a bottleneck for hardware-native implementation. Furthermore, the computational cost of deep learning is rising unsustainably, and the "black box" nature of MLPs limits interpretability. Kolmogorov-Arnold Networks (KANs) offer a theoretical alternative by shifting the computational burden from fixed node activations to learnable nonlinear functions on the network edges. However, efficiently implementing these learnable nonlinearities in hardware without resorting to digital approximations (like Look-Up Tables) or complex circuit-level emulations remains an open challenge.

Methodology
The authors propose a physical analogue KAN architecture (aKAN) that realizes learnable edge functions directly in matter using Reconfigurable Nonlinear-Processing Units (RNPUs).

RNPU Device: The core primitive is a multi-terminal nanoscale silicon device (boron-doped silicon slab with eight electrodes). By applying specific control voltages to its electrodes, the device's steady-state input-output transfer characteristic can be continuously tuned to approximate various nonlinear functions.
Edge Processor (EP): To increase expressivity and precision, multiple RNPUs are combined in parallel within an Edge Processor. The EP sums the scaled outputs of individual RNPUs to form a complex, learned univariate edge function.
Architecture: The aKAN consists of a reconfigurable array of EPs interconnected via programmable switch matrices. Input variables are linearly encoded as voltages, processed through EPs (acting as nonlinear maps), and rescaled for subsequent layers. The system includes mixed-signal interfacing (DACs, ADCs, transimpedance amplifiers) to manage control voltages and readout currents.
Training and Validation: The authors employ a hybrid workflow. They first train the network in software using surrogate models (data-driven MLPs calibrated to experimental RNPU characteristics) to identify optimal control voltages and linear combination coefficients. These parameters are then transferred to the physical hardware for experimental verification. Due to current measurement constraints (single-device setup), multi-RNPU networks are evaluated using time-multiplexing, where a single physical device sequentially emulates the trained RNPUs.

Key Contributions

Hardware-Native Nonlinearity: The paper demonstrates a scalable physical computing primitive where nonlinear edge functions are realized intrinsically by tunable device physics rather than digital emulation.
Reconfigurable Edge Processors: The introduction of the EP, which aggregates multiple RNPUs, allows for the approximation of complex functions (e.g., Bessel functions) that a single device cannot achieve alone.
System-Level Analysis: The authors provide a comprehensive system-level comparison between aKANs and digital fixed-point MLPs, including estimates for energy, silicon area, and latency, accounting for mixed-signal peripheral overhead.
Pruning and Robustness: The study demonstrates that aKANs can be structurally pruned (via L1 regularization on EP gains) to reduce hardware utilization while maintaining performance. It also shows that the architecture is robust to device-to-device variability, as heterogeneous combinations of different physical RNPUs do not degrade approximation accuracy.

Results

Function Approximation: Using experimentally calibrated models and hardware measurements, the aKAN successfully approximates complex functions (sine waves, Bessel functions $J_0(20x)$ ) with Mean Squared Errors (MSE) reaching $\sim 10^{-2}$ or lower. Performance scales with the number of RNPUs per EP.
Regression and Classification: In regression tasks, aKANs achieve performance comparable to software MLP baselines (with ReLU or tanh activations) while often requiring fewer trainable parameters. In binary classification tasks (Moons, Spirals, MAGIC, COD-RNA, Skin Segmentation), aKANs achieve competitive accuracy, sometimes with up to $\sim 5\times$ fewer parameters than ReLU-MLPs.
Hardware Efficiency: System-level estimates for a representative workload ( $e^{\sin(\pi x_1) + x_2^2}$ $e^{s i n (π x_{1}) + x_{2}^{2}}$ ) indicate:
- Energy: Approximately 200 pJ per inference, representing a >100 $\times$ reduction compared to a digital fixed-point MLP at similar error levels.
- Area: A >10 $\times$ reduction in estimated silicon area compared to the digital baseline.
- Latency: An end-to-end inference latency of roughly 0.6 $\mu$ s.
- Note: The authors explicitly state that current energy consumption is dominated by mixed-signal peripheral circuitry (DACs, ADCs, TIAs) rather than the RNPU core itself.

Significance
The paper establishes RNPUs as scalable, hardware-native nonlinear computing primitives. It identifies analogue KAN architectures as a realistic pathway toward energy-, latency-, and footprint-efficient neural network hardware, particularly for edge inference. By shifting the design paradigm from accelerating linear algebra to embedding expressive nonlinear mappings directly in the physical substrate, this work suggests a route to compact, low-power inference where nonlinear computation is native and programmable. The authors emphasize that while the current system is limited by peripheral overhead, future co-design of devices, circuits, and architectures could further unlock the potential of "intelligent matter" for neural computing.