⚡ electrical engineering

Estimating PLL Phase Noise Parameters from Measurements for System-Level Modeling

This paper proposes a least squares method to estimate key Phase-Locked Loop (PLL) parameters, such as oscillator constants and bandwidth, from measured phase noise spectra to enable accurate system-level modeling and compensation for MIMO mobile communication impairments.

Original authors: Carl Collmann, Ahmad Nimr, Gerhard Fettweis

Published 2026-04-10

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CC BY 4.0

Original authors: Carl Collmann, Ahmad Nimr, Gerhard Fettweis

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to conduct a massive orchestra (a 6G mobile network) where every musician (a phone or tower) must play their note at the exact same time and pitch. If even one musician is slightly out of tune or their timing wavers, the whole sound becomes muddy, and the music fails. In the world of wireless signals, this "wavering" is called Phase Noise.

This paper is essentially a guide on how to take a "fingerprint" of that wavering for specific hardware chips and create a perfect digital twin of it, so engineers can predict how bad the music will sound before they even build the orchestra.

Here is the breakdown of the paper using simple analogies:

1. The Problem: The "Wobbly Metronome"

In modern phones and networks, devices use a component called a PLL (Phase-Locked Loop) to keep their timing steady, like a metronome for a drummer. However, no metronome is perfect. It has a tiny, random wobble.

The Issue: If you have one phone, the wobble is annoying. But in 6G, you have hundreds of antennas working together (MIMO). If their wobbles don't match perfectly, the signal cancels itself out, and the connection drops.
The Gap: Engineers know that this happens, but they often don't know exactly how their specific chips wobble. They rely on datasheets (the "manufacturer's promise"), but the paper argues that the reality is often different from the promise.

2. The Solution: The "Digital Twin"

The authors want to create a mathematical model (a digital twin) that mimics the real-world wobble of a specific chip.

The Analogy: Imagine you want to simulate a car crash on a computer. You can't just guess how the metal bends; you need to know the exact strength of the steel and the speed of the impact.
The Method: Instead of guessing, the authors developed a recipe (a Least Squares method) to measure the real chip, analyze the "shape" of its noise, and extract the exact numbers needed to build a perfect simulation.

3. The Experiment: Listening to the "Static"

The team set up a lab to measure two specific chips (MAX2870 and MAX2871) found in popular software-defined radios (USRP).

The Setup: They hooked these chips up to a super-sensitive microphone (a spectrum analyzer) and a GPS clock (to keep a perfect reference).
The Process: They listened to the "static" (noise) coming from the chips across different frequencies.
The "Slope" Trick: They didn't just look at the noise; they looked at how the noise changed as they moved up the frequency ladder. They broke the noise graph into four distinct zones, like climbing a mountain with four different terrains:
1. The Reference Zone: Where the chip copies the master clock.
2. The In-Band Zone: The "flat" area where the chip's own internal noise dominates.
3. The VCO Zone: Where the chip's internal oscillator takes over.
4. The Noise Floor: The absolute bottom limit of silence the chip can reach.

4. The Discovery: Datasheets Lie (Sometimes)

This is the most interesting part. The authors compared their measurements against the official "datasheets" (the instruction manuals) from the chip manufacturer.

The Surprise: The datasheets claimed the two chips were almost identical twins. But when the authors measured them, they found they were actually very different siblings.
- Chip A (MAX2870): Had a "wobbly" in-band noise and a narrow bandwidth (like a drummer who can't keep a fast beat).
- Chip B (MAX2871): Was much cleaner and faster (like a professional drummer).
The Lesson: You cannot trust the "marketing brochure" (datasheet) for high-precision engineering. You must measure the actual hardware to get the truth.

5. The Result: A New Recipe for Engineers

By using their math recipe, the authors extracted specific numbers (like "Oscillator Constants" and "Bandwidth") for these chips.

Why it matters: Now, any engineer designing a 6G system can plug these numbers into their computer simulations. They can say, "If I use the MAX2871 chip, here is exactly how the signal will behave."
The Benefit: This allows them to design compensation systems (software fixes) to cancel out the wobble before they build the physical network, saving time and money.

Summary

Think of this paper as a forensic investigation into the "personality" of electronic chips.

Old way: "The manual says this chip is good, so let's assume it's perfect."
New way: "Let's measure the chip, map out its specific quirks, and build a digital clone that behaves exactly like the real thing."

This ensures that when we build the 6G networks of the future, the "orchestra" stays in tune, and the music (data) flows smoothly.

1. Problem Statement

In next-generation (6G) MIMO mobile communication systems, phase noise is a critical hardware impairment that degrades system performance, particularly by hindering the coherent combination of signals required for beamforming. While phase noise modeling exists in literature, there is a significant gap between theoretical models and practical, hardware-specific implementation:

Lack of Reproducibility: Existing standards (e.g., 3GPP) provide phase noise Power Spectral Density (PSD) models and parameters but often omit the estimation methods used to derive them, making reproduction difficult.
Limited Applicability: Generic models may not apply to different frequencies or specific PLL architectures.
Disconnect between Domains: Many models do not provide a clear link between the frequency-domain PSD and the time-domain phase noise process (often modeled as an Ornstein-Uhlenbeck process), which is necessary for comprehensive system-level simulations.

The paper addresses the need for a reproducible, measurement-based method to extract accurate phase noise parameters from specific hardware to enable realistic time- and frequency-domain simulations.

2. Methodology

The authors propose a Least Squares (LS) estimation method to derive PLL parameters from measured Single-Sideband (SSB) phase noise PSD data. The workflow consists of the following steps:

Measurement Setup:
- Hardware: USRP X310 devices equipped with CBX (MAX2870 PLL) and UBX (MAX2871 PLL) daughterboards.
- Environment: Measurements conducted using an R&S FSQ8 spectrum analyzer locked to a 10 MHz GPS reference (Meinberg 170 MP).
- Configuration: Continuous wave output at 2 GHz (0 dBm). The frequency offset range ( $\Delta f$ ) spans from 100 Hz to 10 MHz.
- Data Processing: PSDs are averaged over 10 observations to reduce variance.
Data Pre-processing & Segmentation:
- The measured PSD is divided into four characteristic regions based on slope analysis using piece-wise linear regression:
  1. Reference Dominant: Low offsets ( $f < 1$ kHz).
  2. PLL In-band Noise Floor: Mid-low offsets ($3$ kHz – $100$ kHz).
  3. VCO Dominant: Mid-high offsets ($300$ kHz – $1$ MHz).
  4. Noise Floor: High offsets ( $f > 3$ MHz).
- Transition regions are excluded to avoid fitting errors near corner frequencies.
Parameter Estimation Model:
- The authors utilize a simplified phase noise PSD model based on an Ornstein-Uhlenbeck (OU) process, represented as a multi-pole/zero model:
  $L(\Delta f) = -10 \log_{10}(\pi f_{c,REF}) + 10 \log_{10} \left[ \frac{1 + (\frac{\Delta f}{\Delta f_{PLL}})^3}{1 + (\frac{\Delta f}{f_{c,REF}})^3} \cdot \frac{1 + (\frac{\Delta f}{\Delta f_{NF}})^3}{1 + (\frac{\Delta f}{B_{PLL}})^3} \right]$
- Estimation Steps:
  - Oscillator Constants ( $c_{REF}, c_{VCO}$ ): Derived by estimating the 3 dB cut-off frequencies ( $f_{c,i}$ ) from the dominant regions (Reference and VCO) using a specific LS estimator derived from the asymptotic behavior of the model.
  - Bandwidths & Noise Levels: The in-band cut-off ( $\Delta f_{PLL}$ ), PLL bandwidth ( $B_{PLL}$ ), and noise floor cut-off ( $\Delta f_{NF}$ ) are calculated by finding the intersection points between the estimated noise floor levels and the modeled filter responses.

3. Key Contributions

Novel Estimation Framework: The paper presents a systematic, least-squares-based method to reverse-engineer PLL model parameters directly from raw measurement data, bridging the gap between hardware measurements and simulation models.
Hardware Validation: The method is applied to two distinct commercial PLL synthesizers (MAX2870 and MAX2871) integrated into USRP SDR platforms, providing a validated dataset for the research community.
Time-Frequency Domain Link: The extracted parameters allow for the generation of phase noise processes that are statistically identical to the measured hardware in both time and frequency domains, facilitating accurate MIMO and sensing simulations.
Open Data: The measurement datasets and the methodology are made available for reproducibility.

4. Key Results

The study successfully extracted parameters for both MAX2870 (CBX) and MAX2871 (UBX) devices. Notable findings include:

Reference Oscillator Consistency: As expected, the reference oscillator parameters ( $f_{c,REF}$ and $c_{REF}$ ) were nearly identical for both boards since they share the same external reference source.
VCO Discrepancy: Despite manufacturer datasheets claiming similar VCO performance (differences < 2 dB), the measurements revealed a significant difference in the VCO oscillator constant:
- MAX2870 (CBX): $c_{VCO} \approx 1.54 \times 10^{-17}$ s
- MAX2871 (UBX): $c_{VCO} \approx 4.28 \times 10^{-17}$ s
- Significance: This highlights that datasheet specifications are insufficient for precise system modeling; empirical extraction is necessary.
In-Band Performance: The MAX2871 (UBX) demonstrated superior in-band noise performance ($-107.8$ dBc/Hz) compared to the MAX2870 ($-91.9$ dBc/Hz), with a wider PLL bandwidth ($177.3$ kHz vs. $26.6$ kHz). This aligns with the MAX2871's higher Phase Frequency Detector (PFD) frequency capability.
Noise Floor: A substantial difference in the noise floor was observed ($-144.4$ dBc/Hz for CBX vs. $-134.0$ dBc/Hz for UBX), likely due to differences in output buffer or power amplifier designs on the daughterboards.
Model Accuracy: The fitted models using the estimated parameters closely matched the measured PSDs, validating the accuracy of the extraction method.

5. Significance and Future Applications

System-Level Simulation: The extracted parameter sets enable engineers to simulate MIMO and Joint Communication and Sensing (JC&S) systems with realistic hardware impairments, leading to more robust algorithm design.
Generalizability: The method is not limited to the tested devices; it can be applied to any PLL frequency synthesizer, allowing designers to create hardware-validated models for their specific components.
Future Work: The authors suggest using this modeling approach to compare simulation results against real-world performance assessments in 6G MIMO and sensing scenarios, potentially optimizing beamforming and sensing algorithms to mitigate phase noise effects.

In conclusion, this paper provides a critical tool for the wireless research community by transforming raw phase noise measurements into actionable, simulation-ready parameters, thereby improving the fidelity of 6G system modeling.