A digitally controlled silicon quantum processing unit

1. The Problem

The realization of commercially viable, utility-scale quantum computers faces two primary bottlenecks:

1. Manufacturability and Scalability: While silicon spin qubits have shown rapid advancements in fidelity due to compatibility with semiconductor manufacturing, scaling them requires integrating thousands of qubits.
2. Control and Wiring Complexity: Current architectures struggle with the "wiring bottleneck." Placing control electronics at room temperature requires routing thousands of high-fidelity analog links, causing thermal load and signal degradation. Placing them at the millikelvin (mK) stage creates excessive heat that destroys qubit coherence.
3. Noise and Error Correction: Achieving the low error rates necessary for Quantum Error Correction (QEC) requires overcoming intrinsic noise (charge and magnetic) and extrinsic noise (control signal miscalibration and crosstalk).

2. Methodology: The Integrated Quantum Processing Unit (QPU)

The authors present a fully integrated system designed to bridge the gap between qubit fabrication and scalable control. The system consists of three core components:

• A. The Qubit Device (Silicon EO Qubits):

  • Architecture: A 54-dot array arranged in three rails, configurable to host up to 18 Exchange-Only (EO) qubits.
  • Encoding: Qubits are encoded in the joint spin state of three electrons (a decoherence-free subsystem), making them robust against global magnetic field fluctuations.
  • Fabrication: Built on a 200-mm Si/SiGe heterostructure using a proprietary foundry process. The device features isotopically enhanced $^{28}$Si and depleted $^{73}$Ge to reduce magnetic noise, and engineered valley splitting to prevent leakage.
  • Performance: The devices exhibit significantly lower intrinsic charge noise compared to previous generations.

• B. The Cryogenic CMOS Controller:

  • Location: Operates at the 4 K stage of a dilution refrigerator.
  • Specs: A custom 130-nm RF CMOS chip containing ~70 million transistors. It generates all time-varying control signals (DACs for voltage, pulse generators for exchange timing).
  • Function: It uses an autonomous multi-sequencer engine (up to 250 MHz) with a custom instruction set to execute complex pulse sequences without real-time room-temperature intervention.
  • Power: Consumes $\leq$ 3.5 W, fitting within the thermal budget of the 4 K stage.

• C. The Superconducting Interconnect:

  • Technology: A high-density superconducting ribbon cable (Nb on polyimide) connecting the 4 K controller to the mK qubit chip.
  • Performance: Routes 296 signal lines (150 time-varying + 35 static biases) with near-end crosstalk < -80 dB at 10 GHz.
  • Thermal: Acts as a thermal standoff, conducting less than 10 $\mu$W from 4 K to mK, preventing the controller from heating the qubit stage.

3. Key Contributions

• System Integration: The first demonstration of a fully integrated silicon QPU combining a custom cryo-controller, a superconducting ribbon interconnect, and a high-density EO qubit array.
• Order-of-Magnitude Improvement: Achieved single-qubit and two-qubit (CNOT) gate errors that are an order of magnitude better than previous state-of-the-art silicon spin qubits.
• Error Correction Validation: Successfully implemented and validated quantum error correction codes, demonstrating that performance scales with circuit complexity rather than degrading.
• Leakage Mitigation: Demonstrated the effectiveness of "Leakage Reduction Units" (LRUs) in preventing the accumulation of errors outside the computational subspace, a critical requirement for long QEC cycles.

4. Key Results

• Gate Fidelity:

  • Single-Qubit Gates: Mean error of $2 \times 10^{-4}$.
  • Two-Qubit (CNOT) Gates: Mean error of $3 \times 10^{-3}$, with the lowest reproducible error reaching $9 \times 10^{-4}$.
  • Noise Characterization: Intrinsic charge noise improved by a factor of 10. Intrinsic device noise contributes only ~0.02% to the CNOT error; the dominant error source is identified as "extrinsic" contextual miscalibration and signal integrity issues, which are manageable.

• Quantum Error Correction (QEC) Demonstrations:

  • Distance-3 and Distance-5 Repetition Codes: Implemented using 7 and 18 qubits respectively.
    • The Distance-5 code showed a logical error rate (LER) of $5.0 \times 10^{-3}$.
    • The scaling factor ($\Lambda_{5/3}$) between distance-3 and distance-5 was 4.7, indicating that error correction is effective and logical errors are suppressed as code distance increases.
    • Leakage: Experiments confirmed that including LRUs stabilizes the detector event fraction, preventing leakage accumulation.
  • [[4,2,2]] Quantum Error Detecting Code:
    • Implemented on 6 physical qubits to detect any single-qubit error.
    • Achieved a logical state fidelity ($F_L$) of 0.95 after post-selection (rejecting shots with detected errors), compared to 0.59 without post-selection.
    • Detector Error Model (DEM) analysis showed "well-behaved" errors with no statistically significant unexpected high-weight events, validating the error model.

• Simulation vs. Experiment:

  • The experimental results aligned closely with simulations that included intrinsic noise (charge/magnetic) and a quasi-static miscalibration model.
  • The agreement confirms that the system behaves predictably and that the fundamental design decisions are sound.

5. Significance and Future Outlook

• Path to Commercialization: This work demonstrates that semiconductor spin qubits can be controlled using a scalable, manufacturable architecture that leverages existing CMOS processes. The system minimizes the "wiring bottleneck" and thermal load, making it a strong candidate for utility-scale quantum computing.
• Error Correction Readiness: By successfully running repetition codes and error-detecting codes with logical fidelities approaching the threshold for fault tolerance, the team has moved silicon qubits from the "noisy intermediate-scale" phase toward the "fault-tolerant" phase.
• Next Steps: The authors identify remaining engineering challenges, including further reducing power consumption per qubit, improving device uniformity to reduce calibration overhead, and refining magnetic hygiene. However, the prototype proves that a utility-scale, fault-tolerant quantum computer is achievable within a single commercial cryostat using this architecture.

In summary, this paper marks a pivotal milestone in silicon quantum computing, proving that a fully integrated, digitally controlled system can achieve the high fidelities and error correction capabilities required for practical, large-scale quantum applications.