E-ReCON: An Energy- and Resource-Efficient Precision-Configurable Sparse nvCIM Macro for Conventional and Spiking Neural Edge Inference

Technical Summary of E-ReCON: An Energy- and Resource-Efficient Precision-Configurable Sparse nvCIM Macro

Problem Statement
The deployment of Artificial Intelligence (AI) workloads, particularly Convolutional Neural Networks (CNNs) and Spiking Neural Networks (SNNs), on resource-constrained edge devices is hindered by the "memory wall" inherent in conventional Von-Neumann architectures. Frequent data movement between memory and processing units results in significant latency and energy overhead. While Compute-in-Memory (CIM) architectures offer a solution by performing computation within the memory array, existing ReRAM-based CIM designs face specific challenges:

1. Analog Limitations: Traditional analog CIM approaches suffer from low signal-to-noise ratios (SNR), sensitivity to process-voltage-temperature (PVT) variations, and the high area/power cost of Analog-to-Digital Converters (ADCs).
2. Digital Overhead: Digital CIM architectures often rely on complex peripheral circuitry or iterative tuning. Furthermore, the accumulation logic (adder trees) in digital CIM often incurs high transistor counts and power consumption, particularly when using conventional Ripple-Carry Adders (RCA).
3. SNN Compatibility: There is a need for architectures that can efficiently handle both conventional CNN workloads and event-driven SNN workloads without requiring distinct hardware or conversion circuitry.

Methodology and Architecture
The authors propose E-ReCON, a 16 Kb digital compute-in-memory (DCIM) macro implemented in 65 nm CMOS technology at 1.2 V. The architecture is built upon three core innovations:

1. 3T1R ReRAM Bitcell:

   • The macro utilizes a compact 3-transistor, 1-resistor (3T1R) ReRAM bitcell occupying only 0.85 µm².
   • It employs a resistive AND-based multiplication scheme where the stored weight (High Resistance State '0' or Low Resistance State '1') interacts with input activations via local transistor logic.
   • This design eliminates the need for ADCs and DACs, enabling fully digital, deterministic computation. The bitcell supports both CNN inference and SNN spike-weight multiplication using the same AND-based operation, leveraging the binary nature of spike activations.

2. Interleaved 10T/28T Adder Tree:

   • To address the accumulation overhead, the authors introduce a novel interleaved adder tree structure.
   • This tree alternates between compact 10-transistor (10T) full adders and conventional 28-transistor (28T) full adders.
   • The 10T adders reduce area and power but introduce voltage degradation due to pass-transistor logic. By interleaving them with 28T adders, the design restores signal integrity at each stage, preventing error propagation while significantly reducing the overall transistor count compared to a pure 28T RCA design.

3. Macro Organization and Mapping:

   • The 16 Kb macro is organized into 64 independent banks, each with 64 rows and 4 columns, supporting 4-bit weight precision per bank.
   • It supports bit-serial input processing (1 to 8 bits), allowing flexible mapping of convolutional and fully connected layers.
   • Peripheral circuitry handles ReLU activation, pooling, and batch normalization, while the removal of ADC/DAC blocks significantly improves throughput.

Key Contributions

• Fully Digital ReRAM-CIM: A deterministic architecture that eliminates iterative tuning and ADC/DAC requirements, ensuring low-latency operation.
• Dual-Purpose Bitcell: The 3T1R AND-type bitcell supports both CNN and SNN workloads, enabling efficient spike-domain accumulation with low switching activity.
• Area-Efficient Accumulation: The interleaved 10T/28T adder tree reduces transistor count by 37% and power consumption by 28% compared to conventional 28T RCA-based designs.
• Robustness: The design maintains reliable digital functionality across all PVT corners (-40°C to 125°C) and under ±20% ReRAM variability (HRS/LRS) without additional error-correction circuitry.

Experimental Results
The proposed macro was evaluated using 65 nm CMOS simulations and mapped to various neural network models:

• Performance Metrics:

  • Latency: Minimum latency of 0.48 ns.
  • Throughput: 2.31 to 3.1 TOPS.
  • Energy Efficiency: Up to 419 TOPS/W (with 30% sparsity).
  • Comparison: The design improves latency and energy efficiency by nearly 30–40% compared to prior state-of-the-art ADC-based ReRAM-CIM designs.

• Inference Accuracy (CNNs):

  • LeNet-5 (MNIST/A-Z): 97.81% accuracy.
  • AlexNet (CIFAR-10): 93.23% accuracy.
  • CNN-8 (SVHN): 96.51% accuracy.
  • Pruning: 40% parameter pruning preserved nearly 99.8% of the original accuracy while reducing MAC operations by 27% and computation cycles by 33%.

• Inference Accuracy (SNNs):

  • The 2A2W (2-bit activation, 2-bit weight) configuration achieved accuracy close to the FP32 baseline across VGG-8, VGG-16, and ResNet-18 on CIFAR-10, CIFAR-100, and ImageNet-1K datasets.
  • Event-driven inference reduced memory accesses and accumulator activity, further enhancing energy efficiency.

Significance and Claims
The paper claims that E-ReCON provides a scalable, low-latency, and energy-efficient non-volatile CIM platform suitable for next-generation edge-AI, IoT, biomedical sensing, and neuromorphic applications. By integrating a compact 3T1R bitcell with an optimized interleaved adder tree, the architecture successfully balances high computational density with robust operation under variability. The ability to support both conventional and spiking neural networks on a single, ADC-less digital macro positions E-ReCON as a viable solution for battery-powered edge devices requiring high efficiency and flexibility.