Technical Summary: AUTOGATE

Problem Statement

Fine-grain clock gating (FGCG) is a critical technique for reducing dynamic power in VLSI systems by suppressing clock signals to idle flip-flop groups. However, current industrial optimization flows rely heavily on manual RTL restructuring to expose workload-dependent gating opportunities that commercial synthesis tools cannot infer automatically.

Recent attempts to automate this process using Large Language Models (LLMs) face two fundamental limitations:

1. Context Limitations: Effective FGCG requires analyzing cycle-accurate switching behavior across millions of clock cycles. Raw waveform traces exceed the context windows of current LLMs, preventing them from directly reasoning about long-term toggling patterns.
2. Scalability: Existing LLM-based optimization approaches are largely confined to small, single-module designs. They fail to scale to large, hierarchical industrial codebases with complex cross-module dependencies, where a single-agent approach cannot coordinate optimization across the entire design hierarchy.

Methodology

The authors present AUTOGATE, the first agentic framework designed for industry-grade RTL power optimization. It employs a Machine Learning (ML) and LLM co-design strategy to bridge waveform-level analysis with RTL rewriting, utilizing a hierarchical multi-agent architecture.

The framework operates in four distinct stages:

1. Hierarchy Detection and Pre-Profiling

AUTOGATE adopts a divide-and-conquer strategy to manage large codebases:

• Hierarchy Parsing: An orchestrator LLM parses the RTL source tree to resolve parent-child relationships and identify independently optimizable modules.
• Power Bottleneck Analysis: The system performs per-module pre-profiling, mapping gate-level power estimates back to RTL regions to rank modules by optimization potential.
• Workload Extraction: To avoid manual testbench creation, AUTOGATE extracts module-level testbenches directly from full-design simulation traces. It parses interfaces and scopes waveform data to generate standalone testbenches that replay realistic workload inputs for specific bottleneck modules.

2. Adaptive Stability-Based FGCG Exploration

This stage replaces raw waveform processing with an ML-driven analysis that guides the LLM:

• Toggle-Aware Pre-Filtering: Registers are partitioned into low, middle, and high toggle-rate bands. Only the "middle" band (registers with moderate activity) is processed for clustering, as extreme values offer little gating benefit.
• Automatic Threshold Discovery: Instead of relying on manually tuned efficiency thresholds, the system computes a group-wise efficiency spectrum to identify natural gaps in gating efficiency, automatically determining optimal clustering thresholds.
• Stability-Based Clustering: Registers are clustered based on their binary stability patterns (sequences indicating whether a register changes state at each clock edge). The algorithm merges clusters only if the logical AND of their stability patterns meets a minimum efficiency threshold.
• Structured Reporting: The clustering results are distilled into compact, structured reports that identify inefficient Integrated Clock Gating (ICG) cells and recommend specific RTL regions for rewriting.

3. LLM-Guided Parallel Rewriting

A multi-agent system executes the optimization:

• Orchestration: An orchestrator assigns modules to sub-agents, scheduling optimization bottom-up (leaves first) to ensure child modules are optimized before parents.
• Rewrite Agents: Dedicated agents use the clustering reports and a library of clock-gating rewrite templates (e.g., enable/hold extraction, value-change-based gating, control-signal factoring, and register decomposition) to generate functionally equivalent RTL variants.
• Iterative Refinement: A reflection agent evaluates power and area trade-offs, distilling lessons into "playbooks" to guide subsequent iterations. Agents generate fine-, medium-, and coarse-grain variants to balance power reduction against area overhead.

4. Formal Verification and QoR-Aware Merge

• Validation: All candidates undergo syntax checking, simulation, commercial formal equivalence checking, and timing validation.
• Selection: Candidates are synthesized to profile dynamic power, area, and timing. The system selects the variant that maximizes dynamic power reduction while adhering to area and timing constraints.
• Hierarchical Merge: Accepted patches are merged hierarchically and re-validated at the parent level.

Key Contributions

1. First Agentic Framework for Industrial RTL: AUTOGATE is the first framework to enable workload-aware FGCG across large, hierarchical codebases using a multi-agent architecture.
2. ML-LLM Co-Design: It addresses the LLM context limitation by using an ML-based clustering algorithm to distill raw waveform traces into structured representations. This allows LLMs to perform RTL rewriting without processing raw switching data directly.
3. Scalability via Divide-and-Conquer: The framework overcomes scalability issues by decomposing complex designs into manageable modules, enabling coordinated optimization while preserving cross-module correctness.
4. Performance Beyond Commercial Flows: The system exposes gating opportunities that commercial synthesis tools with aggressive automatic inference miss, achieving significant power reductions with minimal area overhead.

Experimental Results

The authors evaluated AUTOGATE on 10 designs, including small benchmarks, industrial-grade open-source designs (NVDLA, BlackParrot), and highly optimized proprietary production designs.

• Small Benchmarks: On a suite of small designs, AUTOGATE reduced dynamic power by an average of 49.31% with only 0.15% average area overhead. For example, it reduced the dynamic power of a booth multiplier by 86.21% and a counter by 55.33%.
• Industrial Designs:
  • NVDLA: Achieved 19.34% dynamic power reduction on the total design, with specific partitions showing up to 47.60% reduction under specific workloads.
  • BlackParrot: Achieved 7.96% dynamic power reduction with only 0.04% area overhead.
• Proprietary Production Designs: On highly optimized production designs, AUTOGATE achieved up to 6.86% dynamic power reduction. The study noted that optimizing across multiple workloads ("Combined" strategy) improved robustness and reduced the risk of overfitting to a single workload compared to single-workload optimization.
• Comparison: In all cases, AUTOGATE consistently outperformed baselines using POET (an evolutionary search approach) and ROVER (a rule-based approach), which showed negligible or negative improvements on large hierarchical designs.

Significance and Claims

The paper claims that AUTOGATE demonstrates the viability of ML-LLM co-designed RTL rewriting for industrial-scale power optimization. Its significance lies in:

• Bridging the Gap: Successfully integrating specialized ML analysis for long-sequence waveform data with the reasoning capabilities of LLMs for code generation.
• Scalability: Proving that agentic frameworks can scale from single modules to massive, multi-file industrial repositories without sacrificing correctness.
• Practical Impact: Delivering substantial dynamic power savings on production-grade designs where manual optimization is currently the only alternative, and existing automated tools fail to find workload-dependent opportunities.

The authors modestly acknowledge that the approach relies on workload-derived switching activity and may overfit to specific workloads, particularly in smaller designs. They suggest that future work should focus on the automatic identification of representative workloads to ensure robustness across diverse production use cases.