💻 computer science

Co-Optimization of Analog Kolmogorov-Arnold Networks for Low-Power Function Approximation in Flexible Electronics

This paper introduces hardware-software co-optimized Analog Kolmogorov-Arnold Networks (AKANs) that leverage circuit-aware training and multi-level pruning to achieve up to 55% area and 50% power savings while maintaining high accuracy for complex function approximation in resource-constrained flexible electronics.

Original authors: Paula Carolina Lozano Duarte, Georgios Zervakis, Mehdi Tahoori, Sani Nassif

Published 2026-06-29

📖 4 min read☕ Coffee break read

CC BY 4.0

Original authors: Paula Carolina Lozano Duarte, Georgios Zervakis, Mehdi Tahoori, Sani Nassif

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you have a smartwatch or a health sensor that needs to do math on your body's signals (like your heartbeat or sweat levels) right where the data is collected. Usually, this is a problem because doing complex math requires a lot of power, and these tiny, flexible devices have very little battery to spare.

This paper introduces a clever solution called Analog Kolmogorov-Arnold Networks (AKANs). Here is the breakdown of what they did, using simple analogies:

1. The Problem: The "Heavy Backpack"

Think of traditional digital computing like a backpack full of heavy textbooks. To solve a math problem, the sensor has to:

Take the raw signal (like a heartbeat).
Translate it into digital numbers (0s and 1s) – this is like translating a foreign language.
Crunch the numbers using a digital processor.
Translate the answer back.

This process is slow and eats up a lot of battery. For flexible electronics (like a sticker on your skin), carrying this "heavy backpack" is impossible.

2. The Solution: The "Analog Shortcut"

The authors propose doing the math directly in the analog world (using electricity flowing through wires) before it ever becomes a digital number.

The Analogy: Instead of translating a foreign language and then doing the math, you just do the math using the sounds and tones of the language itself. It's faster and uses less energy.
The Tool: They use a specific type of math structure called a Kolmogorov-Arnold Network (KAN). Imagine a KAN as a set of flexible, stretchy rubber bands (called "splines") that can be shaped to fit almost any curve or pattern in the data.

3. The Innovation: "Trimming the Fat"

The big challenge with these analog circuits is that they aren't perfect. Just like a hand-drawn line isn't perfectly straight, the electrical components have tiny errors due to manufacturing. Also, the circuits can be bulky.

The authors developed a Hardware-Software Co-Optimization method. Think of this as a two-step process:

Step 1: The Simulation (The "Test Drive"): They built a digital twin of their physical circuit and ran thousands of simulations to see exactly how the "rubber bands" behaved in the real world, including all the tiny imperfections.
Step 2: The Pruning (The "Sculpting"): They realized that some parts of the math weren't actually needed.
- Imagine a sculpture made of clay. Some parts of the clay are essential to the shape, but other parts are just excess weight.
- The authors "pruned" (removed) specific mathematical terms (coefficients) that contributed very little to the final shape but took up a lot of space and power.
- The Twist: Usually, removing parts of a model makes it less accurate. But here, because they trained the network while knowing exactly what the "broken" circuit would look like, removing the unnecessary parts actually made the final result more accurate. It's like removing a wobbly leg from a table; the table becomes more stable.

4. The Results: Lighter, Faster, and Better

They tested this on real-world data, such as heart rate monitors (ECG/PPG) and household power usage. The results were impressive:

Size: They reduced the physical size of the circuit by up to 55% (like shrinking a backpack to the size of a wallet).
Power: They cut the energy usage by up to 50% (doubling the battery life).
Accuracy: Surprisingly, the pruned, smaller version was often more accurate than the full, untrimmed version because it removed the "noise" caused by the unnecessary parts.

5. Why It Matters for Flexible Electronics

Flexible electronics (like those made from special plastic or metal foils) are great for wearables, but they are fragile and have strict limits on how much power they can use.

The authors showed that their method works perfectly on IGZO technology (a type of flexible transistor).
They proved that even if the temperature changes or the manufacturing isn't perfect (which happens with flexible chips), the system remains stable and accurate.

Summary

In short, the authors built a "smart sculptor" for electronic circuits. They took a complex math tool, simulated how it would behave on a flexible chip, and then carefully cut away the unnecessary pieces. The result is a tiny, ultra-low-power circuit that can do complex math on your body's signals without draining your battery, and it actually works better because it's simpler.

Technical Summary: Co-Optimization of Analog Kolmogorov-Arnold Networks for Low-Power Function Approximation in Flexible Electronics

Problem Statement
Wearable devices and Internet of Things (IoT) sensors increasingly require on-sensor processing of biosignals and environmental data. These tasks involve computationally demanding operations such as nonlinear activation functions, sensor calibration curves, and signal preprocessing (e.g., logarithmic compression, power operations). Implementing these functions digitally often incurs significant energy overhead due to analog-to-digital conversion (ADC) and subsequent digital processing. While Flexible Electronics (FE) offer a promising platform for wearable applications due to their mechanical flexibility and low-cost fabrication, they impose strict constraints on circuit density and power consumption. Furthermore, analog implementations are vulnerable to noise, process variations, and device mismatches, which can degrade approximation accuracy if hardware non-idealities are not explicitly addressed during model design. Existing approaches, such as RRAM-based computing-in-memory or polynomial-based techniques, face limitations regarding device variability, energy demand, or lack of specific optimization for FE platforms.

Methodology
The authors propose Analog Kolmogorov-Arnold Networks (AKANs), developed through a hardware–software co-optimization methodology. The core of this approach is a unified design loop that integrates circuit simulation, error modeling, and parameter pruning.

Hardware Architecture: The AKAN is implemented using Indium Gallium Zinc Oxide (IGZO) Thin-Film Transistors (TFTs), a unipolar technology suitable for FE. The network utilizes Analog Building Blocks (ABBs) to construct quadratic splines representing the function $B(x) = k_0 + k_1x + k_2x^2$ . These splines are interconnected via Multiply-Accumulate (MAC) operations using resistors to assign weights.
Hardware-Aware Error Modeling: Unlike prior works that assume ideal behavior or use statistical error distributions, this work derives a continuous, input-dependent error function ( $\hat{\epsilon}_{hardware}(x)$ ) directly from transient SPICE simulations of the IGZO circuits. This model captures systematic hardware non-idealities across the full coefficient space ( $k_0, k_1, k_2$ ).
Coefficient-Level Pruning: The methodology introduces a pruning strategy that operates at the level of individual polynomial coefficients rather than entire neurons or splines. Removing a coefficient (e.g., setting $k_1$ to zero) corresponds to the physical removal of specific circuit blocks (multipliers, squarers, or adders).
Co-Design Training: The pruning process is integrated into the KAN training loop. For each pruning configuration, the corresponding hardware error model is injected into the training objective as additive noise ( $f_{target}(x) = f_{ideal}(x) + \hat{\epsilon}_{hardware}(x)$ ). This allows the network to learn parameter configurations that remain robust under realistic operating conditions and specific pruning constraints.

Key Contributions
The paper identifies three primary contributions:

Technology-Aware Analog Error Modeling: The derivation of continuous, input-dependent error functions directly from transient SPICE simulations of unipolar IGZO TFT circuits, capturing systematic hardware non-idealities in a commercially relevant FE process.
Circuit-Block-Level Coefficient Pruning: A pruning methodology that operates on individual polynomial coefficients ( $k_0, k_1, k_2$ ) of each quadratic spline. This approach enables the physical removal of circuit blocks, directly translating software decisions into hardware area and power savings.
Application-Driven Validation: Comprehensive evaluation across four datasets (PPG-DaLiA, ECG5000, Individual Household Electric Power Consumption, and Iris) covering biomedical monitoring and sensing scenarios relevant to FE deployment.

Results
The proposed framework was validated through extensive SPICE simulations and training experiments:

Hardware Efficiency: Pruning individual coefficients resulted in significant hardware savings. The best-case scenarios demonstrated up to 55% area reduction and 50% power reduction compared to the unpruned baseline. On average, reductions across datasets were nearly 30% for both metrics.
Accuracy Improvements: Contrary to the expectation that pruning degrades performance, the results showed that pruning could improve approximation accuracy. The removal of near-zero coefficients acted as an implicit regularizer, reducing the model's susceptibility to overfitting and hardware noise. In several cases, the pruned AKAN achieved lower Normalized Mean Percentage Error (NMPE) than the unpruned baseline.
Robustness: A PVT (Process, Voltage, Temperature) analysis across 27 operating corners confirmed that the hardware-aware training compensates for systematic shifts. The NMPE remained stable within the wearable temperature range (27–40°C), with a maximum deviation of only 0.74 percentage points relative to nominal conditions.
Downstream Performance: When evaluated on downstream tasks (classification for ECG5000 and Iris; signal reconstruction for IHEPC and PPG-DaLiA), the pruned AKANs maintained performance comparable to the unpruned baseline and ideal software-only KANs. In signal reconstruction tasks, the best pruned configurations even outperformed the unpruned hardware baseline, reducing NRMSE by up to 33%.

Significance
The paper claims that this work establishes a robust and generalizable framework for low-power analog function approximation in Flexible Electronics. By explicitly accounting for circuit-level constraints during training and employing a coefficient-level pruning strategy, the proposed AKANs address the critical trade-off between hardware efficiency and approximation accuracy. The results demonstrate that strategic parameter reduction does not merely save resources but can enhance the generalization capability of analog neural networks, making them viable for resource-constrained, real-time sensing applications in wearables and IoT. This approach offers a pathway to implementing complex nonlinear functions directly in analog hardware without the prohibitive area and power costs typically associated with such implementations in FE technologies.