💻 computer science

CSCO: A Backside-PDN-Aware Clock-Signal Co-Optimization Framework for Improved PPA

This paper proposes CSCO, a data-driven framework that jointly optimizes clock and signal net allocation across frontside and backside power delivery networks to balance IR-drop, congestion, and signal integrity, thereby improving overall PPA without additional shielding overhead.

Original authors: Zixiao Wang, Leilei Jin, Zhen Zhuang, Rongmei Chen, Bei Yu

Published 2026-07-16

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CC BY 4.0

Original authors: Zixiao Wang, Leilei Jin, Zhen Zhuang, Rongmei Chen, Bei Yu

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine the inside of a computer chip as a bustling, high-tech city. For decades, this city has been built on a single, flat plane where the roads (wires) carry data, and the power lines (electrical grids) run alongside them, often getting in the way. As technology shrinks to the size of a few atoms, this city is becoming dangerously crowded. The roads are jammed, causing traffic jams that slow down information, and the power lines are so thin and far away that the electricity struggles to reach the buildings, causing "brownouts" (voltage drops) that make the city flicker.

To fix this, engineers came up with a clever idea: move the power grid to the "backside" of the silicon wafer, like building a massive underground subway system beneath the city. This frees up the surface for more roads and makes power delivery super efficient. However, this new underground world has a catch. It's not just a power grid; it's also a limited resource that needs to be shared between the city's most important traffic (the clock signals that keep everything in sync) and the regular data traffic. Furthermore, without the power lines sitting right next to the data roads on the surface, the data signals start getting noisy, like trying to talk in a room where the walls have been removed and everyone is shouting. The big question is: how do we split this limited underground space between the clock and the data, and how do we keep the noise down, without getting lost in a maze of trial and error?

This is the challenge tackled by a new framework called CSCO (Clock–Signal Co-Optimization), proposed by researchers Zixiao Wang, Leilei Jin, and their team. Instead of treating the clock and data networks as separate problems or guessing where to put them, CSCO acts like a super-smart city planner that figures out the perfect balance for both at the same time.

The researchers found that previous methods were too rigid. Some tried to move only the clock network underground, while others moved only the data, or they assumed the power grid was already set in stone. The paper argues that these approaches miss the big picture because the clock and data networks compete for the same limited underground space, and the power grid's layout directly affects how much room is left for them. If you give too much space to the clock, the data gets congested; if you give too much to the data, the clock gets slow. Worse, simply moving things underground without a plan makes the "noise" problem much worse, causing signals to interfere with each other more than before.

To solve this, CSCO uses a "data-driven" approach. Instead of running thousands of slow, expensive simulations to test every possible combination of where to put wires, the team trained a lightweight, fast "surrogate model." Think of this model as a crystal ball that has learned to predict how a chip will perform based on a few key clues, without needing to build the whole city first. This allows the system to quickly explore millions of different ways to split the underground resources between the clock and the data.

The results from their simulations on realistic chip designs (like a SHA256 processor, a JPEG encoder, and an ARM Cortex-A7 CPU) are promising. The framework successfully found a "sweet spot" where the chip runs faster and more efficiently. For example, on the ARM Cortex-A7 design, CSCO helped boost the effective frequency to 1.96 GHz, a significant jump compared to previous methods. It also managed to reduce the number of wires that suffered from severe noise interference (voltage bumps and delay spikes) by over 80% in some cases, all without adding extra shielding or area.

Crucially, the paper highlights that CSCO doesn't just pick a random spot; it actively uses the backside power lines as a shield. By routing the most noise-sensitive signals right next to the power lines on the backside, the framework blocks out the interference that would otherwise ruin the signal. The team demonstrated that this approach works across different chip designs and power grid configurations, finding the best trade-off between power stability, speed, and signal clarity. While these results come from simulations and custom design flows rather than physical silicon chips, the data suggests that this co-optimization strategy is a powerful way to navigate the complex trade-offs of next-generation chip design, turning a crowded, noisy underground city into a well-orchestrated, high-speed metropolis.

Technical Summary: CSCO – A Backside-PDN-Aware Clock–Signal Co-Optimization Framework

1. Problem Statement

As semiconductor technology scales into the sub-3nm era, physical design faces critical bottlenecks in routing congestion, IR-drop, and signal integrity (SI). Backside Power Delivery Networks (BSPDN) have emerged as a solution to alleviate IR-drop by relocating power grids to the wafer backside via nano-through-silicon-vias (nTSVs), thereby freeing frontside metal layers for signal routing. However, this architectural shift introduces three fundamental challenges that prior works have failed to address comprehensively:

Decoupled Optimization: Existing methods optimize clock and signal networks in isolation. Some focus solely on relocating clock trees, while others migrate signal nets based on geometric heuristics assuming a fixed clock tree. This fails to explore the critical trade-off space of limited backside resources between clock and signal nets.
Interdependent PDN and Routing: Current approaches often presuppose fixed power grid configurations before net selection. In reality, backside net routing and PDN configuration are inherently dependent; routing engines ignore PDN-induced blockages, and PDN synthesis ignores routing demands, fragmenting the design space.
Signal Integrity Degradation: Removing frontside power-ground (P/G) grids eliminates the electromagnetic shielding between signal nets. This creates a "gravity-less" coupling environment where crosstalk increases by 2–4×, leading to severe delta-delay and voltage bumps that can negate the timing benefits of BSPDN.

2. Methodology: The CSCO Framework

The authors propose CSCO, a data-driven, BSPDN-aware co-optimization framework that jointly determines the BSPDN topology and the allocation of signal and clock nets across frontside and backside layers. The framework operates through a unified flow comprising three core components:

A. Problem Formulation

The objective is to determine the optimal binary allocation of nets ( $x_i \in \{0, 1\}$ ) to the backside, maximizing timing performance (WNS and TNS) under BSPDN-dependent constraints.

Objective Function: Maximize $T_{wns} + \lambda T_{tns}$ .
Constraint: A global nTSV budget constraint ( $\sum t_i x_i \le B$ ), where $t_i$ is the pin count of net $i$ . The budget $B$ is empirically determined by identifying the inflection point where increasing nTSVs improves timing but eventually degrades routability.

B. Data-Driven Surrogate Modeling

To avoid the computational prohibitions of full-routing and sign-off timing analysis for every candidate solution, CSCO employs a Factorization Machine (FM) as a surrogate model.

Low-Rank Interaction: The model uses second-order interactions to capture pairwise dependencies between nets (e.g., clock-signal interactions on critical paths) with $O(nl)$ complexity.
Cold-Start Strategy: An empirical scoring model based on post-global-routing metrics (e.g., transition delay, load count, critical path rank) is used to generate an initial diverse dataset for training the FM.
Generalization: Once trained, the FM generalizes across different BSPDN configurations without retraining, as it encodes intrinsic inter-net relationships rather than configuration-specific parameters.

C. Optimization and Inference

The framework operates in two phases:

Training Phase: Uses a greedy selection strategy enhanced by random replacement to collect diverse partitioning samples, ensuring broad coverage of the design space for the surrogate model.
Inference Phase: Utilizes the trained FM to guide a greedy selection followed by Simulated Annealing (SA). The SA process swaps nets between frontside and backside to refine the solution, accepting updates based on the FM-predicted performance.

D. Signal Integrity (SI) Mitigation

Recognizing that BSPDN increases crosstalk, CSCO includes a dedicated SI mitigation stage.

Identification: Nets with voltage bump or delta-delay ratios exceeding specific thresholds (e.g., 40%) are flagged as SI-critical.
Shielding: These critical nets are explicitly reassigned to backside routing tracks where the BSPDN power layers act as electromagnetic shields, suppressing aggressor-victim coupling without requiring additional shielding overhead.

3. Key Contributions

Unified Co-Optimization Framework: The first methodology to concurrently synthesize dual-side signal and clock networks under BSPDN constraints, integrating routing and power delivery planning.
Data-Driven Surrogate Modeling: A scalable optimization scheme using low-rank statistical modeling (Factorization Machines) to capture timing-resource interactions without costly full-routing evaluations.
SI Mitigation via BSPDN Shielding: A novel approach exploiting the electromagnetic properties of BSPDN power layers to protect SI-critical paths, addressing the specific degradation caused by the removal of frontside shields.
Demonstrated Effectiveness: Validation on realistic CPU benchmarks showing significant improvements in PPA metrics while satisfying power and signal integrity constraints.

4. Experimental Results

The framework was evaluated on three benchmarks (SHA256, JPEG, ARM Cortex-A7) using a 7nm technology node.

PPA Improvements:
- Timing: CSCO improved Worst Negative Slack (WNS) by up to 85% (ARM Cortex-A7) and Total Negative Slack (TNS) by 35–70% compared to baselines.
- Frequency: Effective frequency increased by 20% for SHA256 (reaching 1.78 GHz) and 36.1% for ARM Cortex-A7 (reaching 1.96 GHz) compared to frontside-only routing.
- Resource Efficiency: CSCO achieved these gains with fewer nTSVs than competing methods (e.g., DAC25) and negligible area overhead.
Signal Integrity:
- Replacing FSPDN with naive BSPDN increased SI violations (delay and bump) significantly. CSCO reduced total SI violations by 80.5% (delay) and 88.1% (voltage bump) across benchmarks.
- Eye diagram analysis on the worst-case net showed normalized eye width and height improving from 15%/23% (frontside) to 95%/97% (double-sided with CSCO), enabling robust high-frequency operation.
Surrogate Model Efficiency:
- The FM model achieved an $R^2$ of 0.858 and RMSE of 0.0141 ns against sign-off data.
- Evaluation time was reduced from ~323 seconds (PrimeTime) to <30 ms per assignment, offering over 10,000× speedup.
- The model converged with as few as 200–500 training samples.
Joint Optimization:
- CSCO successfully navigated the trade-offs between different BSPDN configurations (varying power rail widths and pitches), identifying Pareto-efficient solutions that balance IR-drop, routing congestion, and timing.

5. Significance and Claims

The paper claims that CSCO establishes a unified methodology for next-generation Design-Technology Co-Optimization (DTCO) and 3D IC integration. Its primary significance lies in:

Breaking Decoupling: Moving beyond isolated clock or signal optimization to a holistic view of backside resource allocation.
Addressing the SI Gap: Explicitly solving the signal integrity degradation inherent to BSPDN by using the power grid itself as a shield, rather than treating SI as a secondary concern.
Scalability: Providing a data-efficient path to explore the complex, coupled design space of 3D ICs without the prohibitive cost of full sign-off iterations at every step.

The authors conclude that CSCO enables the discovery of design-specific optimal solutions that balance power integrity, routing congestion, and timing closure, which were previously unattainable with existing isolated approaches.