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Mitigating the Impact of Retention Loss on Inference Accuracy in 65 nm Single-Poly Floating-Gate Analog In-Memory Computing

This paper demonstrates through experiments on a 65 nm single-poly floating-gate analog in-memory computing array and system-level simulations that combining circuit-level compensation with algorithmic batch normalization recalibration can recover inference accuracy within 2–4% of the baseline after 60 days of retention loss.

Original authors: Mirko Brazzini, Giulio Filippeschi, Alessandro Catania, Sebastiano Strangio, Giuseppe Iannaccone

Published 2026-07-29

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CC0 1.0

Original authors: Mirko Brazzini, Giulio Filippeschi, Alessandro Catania, Sebastiano Strangio, Giuseppe Iannaccone

Original paper dedicated to the public domain under CC0 1.0 (http://creativecommons.org/publicdomain/zero/1.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine a world where your computer doesn't just crunch numbers in a factory, but thinks like a brain, using electricity to mimic the way neurons fire. This is the realm of Analog In-Memory Computing. Instead of shuttling data back and forth between a memory bank and a processor (which is like running to the kitchen every time you need a spoon), this technology stores the "weights" of a neural network—the brain's memories and lessons—right inside the memory cells themselves. It's like having a library where the books can also do the math for you.

However, there's a catch. These memory cells are often made of tiny, floating islands of electric charge. Over time, just like a leaky balloon slowly losing air, these cells naturally lose their charge. This is called retention loss. In a digital world, a little bit of lost charge might just flip a 0 to a 1, which is easy to fix. But in this analog brain, the charge is the answer. If the charge drifts, the math gets wrong, and the computer might mistake a cat for a toaster. Scientists are desperate to figure out how to keep these "leaky" memory brains accurate for months or years, because if they can't, this super-efficient technology will never leave the lab.

This paper dives into that exact problem using a specific type of memory chip built with standard 65 nm technology (a common manufacturing size). The researchers, Mirko Brazzini and his team, wanted to see if they could stop a neural network from forgetting its lessons as the memory cells slowly leaked charge over time. They didn't just guess; they built a real chip, programmed it, and watched what happened over 60 days.

The team discovered that the charge loss happens in two distinct ways, like two different kinds of weather affecting a garden. First, there is a systematic drift, where every cell loses charge in a predictable, average way, shifting the whole garden's growth in one direction. Second, there is stochastic noise, a chaotic, random jitter where some cells lose a little more and some a little less, creating a messy, unpredictable pattern.

To fix this, the team tried two different tools, like a gardener using both a sprinkler and a fertilizer. The first tool was circuit-level compensation. They realized that by simply adjusting the "read voltage" (the pressure used to check the memory), they could counteract the predictable, average drift. It's like turning up the volume on a radio to compensate for a signal that's getting slightly quieter for everyone. The second tool was algorithmic recalibration, specifically something called Batch Normalization Recalibration (BNR). This is a software trick that re-tunes the neural network's internal settings to handle the random, chaotic noise that the voltage adjustment couldn't fix. It's like teaching the brain to ignore the static on the radio and focus on the song.

The results were promising. When they tested their system on two different neural networks (VGG-10 and WideResNet-28-10) trained to recognize images, they found that doing nothing was a disaster; after 60 days, the accuracy plummeted. Using just the voltage adjustment helped, but the network still struggled with the random noise. Using just the software recalibration helped with the noise but missed the big drift. However, when they combined both the voltage adjustment and the software recalibration, the system was a hero. In their simulations, which were calibrated with real experimental data, the network recovered its baseline accuracy to within just 2-4% even after 60 days.

The paper is careful to note that this isn't a magic wand that solves everything forever. The results are based on system-level simulations that were carefully tuned to match real-world measurements from their 65 nm chip. They explicitly show that you cannot rely on just one method; you need both the hardware fix and the software fix to get the job done. While the paper doesn't claim this is a solved problem for all future computers, it demonstrates a clear, practical path forward. It suggests that with these combined techniques, floating-gate analog chips could potentially run reliable, long-term inference tasks for deep learning, keeping their "memories" sharp for at least two months without needing a reset.

Technical Summary: Mitigating the Impact of Retention Loss on Inference Accuracy in 65 nm Single-Poly Floating-Gate Analog In-Memory Computing

Problem Statement
Analog In-Memory Computing (AIMC) using vector-matrix multipliers (VMM) offers significant energy efficiency gains for deep learning by reducing data movement and utilizing sub-threshold operation. While Floating-Gate (FG) memories are a promising candidate due to their compatibility with mature CMOS processes and intrinsic multi-level programmability, they suffer from retention loss. Unlike digital memories where charge loss leads to discrete bit errors, analog memories store synaptic weights as continuous charge levels. Consequently, charge loss perturbs the computation itself, degrading inference accuracy. The challenge lies in assessing and mitigating both the systematic (average) drift and the stochastic (device-to-device) variability of this charge loss over time to maintain reliable neural network performance.

Methodology
The authors conducted experiments and system-level simulations using a single-poly FG analog non-volatile memory array fabricated in a standard 65 nm TSMC CMOS process. The architecture employs a 1T-1FG crossbar scheme where 1T-1FG cells act as programmable current sources.

Device Characterization: The study characterized the retention behavior of memory cells programmed to various current levels (0.4 to 80 nA). Measurements were taken after 10, 30, and 60 days of room-temperature storage. The data revealed that charge loss results in a reduction of the transistor threshold voltage, causing a corresponding increase in programmed current.
Modeling: The retention loss was decomposed into two components:
- Systematic Drift: An average shift in current over time, modeled by fitting the log-log relationship between initial and retained currents to extract slope ( $m$ ) and intercept ( $q$ ) parameters.
- Stochastic Variability: A random, device-to-device variation around the average drift, modeled as a zero-average normal distribution ( $\chi$ ) with a standard deviation ( $\sigma$ ) dependent on the programmed current and time.
Mitigation Strategies: Two complementary techniques were evaluated:
- Circuit-Level Compensation ( $V_{read}$ Compensation - VRC): An adaptive read voltage is adjusted to compensate for the systematic average drift of the threshold voltage.
- Algorithmic Recalibration (Batch Normalization Recalibration - BNR): The mean and variance parameters of batch normalization layers are updated using a calibration dataset. This compensates for the distribution shifts caused by the zero-average stochastic charge loss component.
System Evaluation: The calibrated retention models were integrated into a hardware-aware inference simulation framework. The impact on inference accuracy was evaluated for two neural network architectures: VGG-10 on CIFAR-10 and WideResNet-28-10 on CIFAR-100. Simulations included 500 Monte Carlo runs to account for stochastic variability.

Key Results
The study compared four scenarios: No Mitigation (NM), VRC only, BNR only, and the combined VRC+BNR approach.

Baseline Performance: Without mitigation, inference accuracy degraded significantly over 60 days. For VGG-10/CIFAR-10, accuracy dropped from a reference of 93.7% to 59.6% (BNR only) or lower without any compensation.
Effectiveness of Combined Mitigation: The combination of $V_{read}$ $V_{r e a d}$ compensation and BNR proved highly effective. After 60 days:
- VGG-10/CIFAR-10: Accuracy recovered to 91.4% (reference 93.7%), a deviation of less than 2.5%.
- WideResNet-28-10/CIFAR-100: Accuracy recovered to 78.3% (reference 82.1%), a deviation of approximately 3.8%.
Necessity of Both Techniques: The results demonstrated that neither technique alone was sufficient to restore baseline accuracy. $V_{read}$ compensation addressed the average drift but could not correct the stochastic variability, while BNR addressed the distribution shifts but could not fully correct the systematic offset without voltage adjustment.

Significance and Claims
The paper claims to demonstrate that it is possible to successfully mitigate the impact of retention loss on inference accuracy degradation for deep neural networks using floating-gate analog memory. By combining circuit-level adaptive read voltage adjustments with algorithmic batch normalization recalibration, the authors show that stable inference accuracy can be maintained for over two months (60 days) post-programming.

The significance lies in providing a practical path toward reliable long-term operation of FG-based analog neuromorphic chips. The work establishes that a device-to-system analysis, which accounts for both systematic and stochastic retention components, is essential for deploying analog non-volatile memories in deep learning inference applications. The authors conclude that these techniques enable the recovery of baseline inference accuracy within 2-4% after 60 days, validating the viability of FG technology for AIMC despite inherent retention challenges.

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