⚡ electrical engineering

Hardware-Aware Deployment of Joint SAR Compression and Despeckling on FPGA

This paper bridges the gap between advanced learned SAR compression-despeckling algorithms and spaceborne constraints by successfully deploying and evaluating a joint framework on an FPGA, revealing that replacing GDN activations with ReLU and simplifying model topology significantly improves quality and energy efficiency for onboard Earth observation.

Original authors: Cédric Léonard, Francescopaolo Sica, Martin Schulz

Published 2026-08-13

📖 4 min read☕ Coffee break read

CC BY 4.0

Original authors: Cédric Léonard, Francescopaolo Sica, Martin Schulz

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Imagine you are trying to send a giant, high-definition photo of the Earth from a satellite zooming around in space. The problem is that the satellite is moving so fast and the data is so huge that the "internet" connection back to Earth (the downlink) can't keep up. It's like trying to pour a swimming pool of water through a drinking straw; most of the data would just get stuck in space. To fix this, engineers need to shrink the data before sending it, a process called compression. But there's a catch: the satellite is a tiny, fragile robot with very limited battery power and no room for a massive supercomputer. It can't run the heavy software that usually does the best shrinking.

This is where a clever trick called "Learned Image Compression" comes in. Instead of using old, rigid rules to shrink files, scientists train a digital brain (a neural network) to learn how to compress images efficiently, much like how a human learns to summarize a long story into a short paragraph. However, the photos taken by these satellites aren't like normal pictures. They are taken using radar, which bounces microwaves off the ground. This creates a grainy, static-like noise called "speckle," which looks like salt-and-pepper sprinkled over the image. If you try to compress a noisy photo, the computer wastes its brainpower trying to save the noise instead of the actual picture. The goal of this research is to teach a digital brain to do two things at once: clean up the grainy noise (despeckling) and shrink the file size, all while running on a tiny, low-power chip that can survive the harsh environment of space.

The researchers in this paper, led by Cédric Léonard and his team, decided to test if this "do-it-all" digital brain could actually run on a real piece of space hardware. They chose a specific type of computer chip called an FPGA (Field-Programmable Gate Array), which is like a Lego board for electronics that can be reconfigured to do specific jobs. They took a complex AI model designed for cleaning and compressing radar images and tried to force it to fit onto this chip. The chip had strict rules: it couldn't handle certain types of math operations, it only understood whole numbers (not decimals), and it had to be incredibly energy-efficient.

The team discovered something surprising while trying to make the model fit. The original design used a fancy math tool called "GDN" to help the AI understand the image, but the chip didn't support it. So, they swapped it out for a much simpler tool called "ReLU." They expected this to make the image quality worse, but instead, it actually made the compressed radar images look better. It turns out that the rules for compressing normal photos (like selfies) don't always apply to radar photos; what works for a sunny landscape might not work for a grainy radar scan.

They also tested different versions of the AI brain. Some versions had extra "residual blocks," which are like adding more layers of thinking to the brain. The team found that these extra layers made the computer work ten times harder but only gave a tiny, barely noticeable improvement in picture quality. It was like adding a turbo engine to a bicycle; it burned a lot more fuel but didn't make you go much faster. Because of this, they suggested that for space missions, the simpler, lighter version of the model is the best choice.

Finally, they measured how much energy the chip used compared to a standard computer processor (CPU) and a graphics card (GPU). The FPGA chip was the clear winner, using 11 to 17 times less energy than the CPU and 2 to 6 times less than the GPU. This is a huge deal for satellites, which have very strict power budgets. While the chip wasn't the fastest at processing the images, it was by far the most efficient, proving that it's possible to run these advanced AI cleaning and shrinking tools directly on a satellite without needing a massive power supply. The paper concludes that while there is still work to be done to make this a perfect, ready-to-launch system, they have successfully built a working prototype that shows the future of space-based image processing is not just possible, but efficient.

Technical Summary: Hardware-Aware Deployment of Joint SAR Compression and Despeckling on FPGA

Problem Statement
Next-generation Synthetic Aperture Radar (SAR) missions face a critical bottleneck: data generation rates far exceed downlink capabilities, necessitating efficient onboard data reduction. While Learned Image Compression (LIC) offers superior rate-distortion performance compared to traditional handcrafted codecs (e.g., Block Adaptive Quantization), applying these deep learning models to SAR imagery is challenging due to multiplicative speckle noise. Furthermore, deploying complex neural compression architectures on spaceborne systems is hindered by strict power, compute, and operational constraints. Existing solutions often lack the radiation tolerance and energy efficiency required for space, while hardware-specific adaptations for Field-Programmable Gate Arrays (FPGAs) remain underexplored for joint despeckling and compression tasks.

Methodology
The authors investigate the deployability of a joint SAR Despeckling and Data Compression (DDC) framework on an embedded ZCU102 FPGA-based platform (AMD Zynq UltraScale+ MPSoC). The study utilizes the AMD Vitis AI overlay accelerator, which enforces specific hardware constraints: 8-bit integer (int8) arithmetic and a restricted set of supported operators.

To bridge the gap between theoretical models and hardware reality, the authors perform a systematic ablation study across four model topologies:

FP (Factorized Prior): A baseline autoencoder without hyperpriors or residual blocks.
ResFP: FP with residual blocks.
SH (Scale Hyperprior): Includes a hyperprior branch to model latent dependencies.
ResSH: The original DDC architecture (SH with residual blocks and Generalized Divisive Normalization - GDN).

The methodology involves a "hardware-aware redesign" where the original ResSH architecture is modified to comply with FPGA constraints:

Activation Functions: GDN layers are replaced with ReLU, as GDN is unsupported by the Vitis AI Deep Learning Processing Unit (DPU).
Convolutional Layers: Transposed convolution kernels are reshaped from $(5 \times 5, 2, 1)$ to $(4 \times 4, 1, 0)$ to remove unsupported non-zero output padding.
Execution Pipeline: The inference graph is segmented; neural transforms (encoder/decoder) run on the DPU, while entropy encoding/decoding runs on the embedded ARM CPU.
Quantization: Models are quantized from float32 to int8 using Post-Training Quantization (PTQ).

The evaluation compares these models across CPU, GPU, and FPGA platforms, analyzing Rate-Distortion (RD) performance, computational complexity, latency, and energy efficiency.

Key Contributions

First FPGA Deployment: This work presents the first deployment of a joint SAR despeckling and learned compression framework on an FPGA-based embedded platform.
Hardware-Aware Redesign: The authors demonstrate that modifications driven by hardware constraints (replacing GDN with ReLU, adjusting kernel padding) do not degrade performance; surprisingly, they improve the rate-distortion tradeoff.
Architectural Trade-off Analysis: A systematic study reveals that residual blocks offer negligible representational benefits (approx. 0.75 dB improvement) at a tenfold increase in computational cost, suggesting they are inefficient for this specific task.
Cross-Platform Characterization: The study identifies that while GPUs offer the lowest latency, FPGAs are significantly more energy-efficient (11–17× less energy per patch than CPU, 2–6× less than GPU).
Quantization Insights: The paper analyzes the impact of int8 quantization, noting that while it slightly alters structural metrics (EPD), it can result in lower pixel-wise errors (MSE/PSNR) on average due to smoother, desaturated reconstructions that better match despeckled references in dark regions, though this effect penalizes high-scatterer areas.

Results

Performance: Replacing GDN with ReLU improved the RD tradeoff by $1.67 \pm 0.10$ dB at high bitrates. The lightweight FP architecture (without residual blocks or hyperpriors) was identified as the optimal choice for onboard deployment, offering comparable performance to heavier models with significantly lower memory footprint and latency.
Efficiency: The FPGA platform consumed 9.8–12.7 W of active power, well within the typical 20–95 W budget of SmallSat payloads. In terms of energy efficiency, the FPGA outperformed both CPU and GPU baselines by a wide margin.
Latency: While the GPU achieved the lowest latency, the FPGA's parallelization of the real and imaginary channel processing ( $ga(Re^2) \parallel ga(Im^2)$ ) demonstrated effective use of DPU cores, reducing latency by up to 48.7% compared to sequential execution.
Quantization Effects: The int8 models deployed on the FPGA generally showed higher PSNR than float32 GPU baselines at high bitrates on the test set average. However, the paper clarifies this is an artifact of the quantization-induced smoothing effect which reduces pixel-wise errors in dark regions; conversely, on high-scatterer scenes (e.g., the Hamburg tile), the FP int8 model scored lower PSNR than its float32 counterpart, while the more robust ResSH model showed a small gain.

Significance and Claims
The paper explicitly states it does not aim to establish a new state-of-the-art compression algorithm. Instead, its significance lies in providing a functioning edge deployment workflow and an evidence-based starting point for onboard SAR compression. The authors argue that their findings challenge design principles established for natural image compression (e.g., the necessity of GDN or residual blocks) when applied to SAR data. By demonstrating that hardware-aware modifications can preserve or even improve performance while enabling efficient embedded execution, the work sets a foundation for future practical onboard SAR processing systems, highlighting the FPGA as the most energy-efficient platform for this application despite its latency limitations compared to GPUs.

Technical Summary: Hardware-Aware Deployment of Joint SAR Compression and Despeckling on FPGA

More like this